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02dd192e99
This is a tiny patch with a big pile of test changes. This partially fixes PR27885: https://llvm.org/bugs/show_bug.cgi?id=27885 My motivating case looks like this: - vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2] - vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] - vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] + vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] And this happens several times in the diffs. For chips with domain-crossing penalties, the instruction count and size reduction should usually overcome any potential domain-crossing penalty due to using an FP op in a sequence of int ops. For chips such as recent Intel big cores and Atom, there is no domain-crossing penalty for shufps, so using shufps is a pure win. So the test case diffs all appear to be improvements except one test in vector-shuffle-combining.ll where we miss an opportunity to use a shift to generate zero elements and one test in combine-sra.ll where multiple uses prevent the expected shuffle combining. Differential Revision: https://reviews.llvm.org/D27692 llvm-svn: 289837
78 lines
2.8 KiB
LLVM
78 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s
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; Check that we perform a scalar XOR on i32.
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define void @pull_bitcast(<4 x i8>* %pA, <4 x i8>* %pB) {
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; CHECK-LABEL: pull_bitcast:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl (%rsi), %eax
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; CHECK-NEXT: xorl %eax, (%rdi)
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; CHECK-NEXT: retq
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%A = load <4 x i8>, <4 x i8>* %pA
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%B = load <4 x i8>, <4 x i8>* %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, <4 x i8>* %pA
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ret void
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}
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define <4 x i32> @multi_use_swizzle(<4 x i32>* %pA, <4 x i32>* %pB) {
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; CHECK-LABEL: multi_use_swizzle:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],mem[1,2]
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; CHECK-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,3,2,2]
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; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,0,2]
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; CHECK-NEXT: vxorps %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: retq
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
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%S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
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%R = xor <4 x i32> %S1, %S2
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ret <4 x i32> %R
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}
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define <4 x i8> @pull_bitcast2(<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
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; CHECK-LABEL: pull_bitcast2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: movl %eax, (%rdx)
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; CHECK-NEXT: xorl (%rsi), %eax
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; CHECK-NEXT: vmovd %eax, %xmm0
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; CHECK-NEXT: movl %eax, (%rdi)
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; CHECK-NEXT: retq
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%A = load <4 x i8>, <4 x i8>* %pA
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store <4 x i8> %A, <4 x i8>* %pC
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%B = load <4 x i8>, <4 x i8>* %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, <4 x i8>* %pA
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ret <4 x i8> %C
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}
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define <4 x i32> @reverse_1(<4 x i32>* %pA, <4 x i32>* %pB) {
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; CHECK-LABEL: reverse_1:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: retq
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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define <4 x i32> @no_reverse_shuff(<4 x i32>* %pA, <4 x i32>* %pB) {
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; CHECK-LABEL: no_reverse_shuff:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
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; CHECK-NEXT: retq
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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