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eb66b33867
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
169 lines
6.4 KiB
C++
169 lines
6.4 KiB
C++
//===-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp - Call lowering -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPUCallLowering.h"
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#include "AMDGPU.h"
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#include "AMDGPUISelLowering.h"
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#include "AMDGPUSubtarget.h"
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#include "SIISelLowering.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "This shouldn't be built without GISel"
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#endif
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AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
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: CallLowering(&TLI), AMDGPUASI(TLI.getAMDGPUAS()) {
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}
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bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MIRBuilder.buildInstr(AMDGPU::S_ENDPGM);
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return true;
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}
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unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
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Type *ParamTy,
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unsigned Offset) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const SIRegisterInfo *TRI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const Function &F = *MF.getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUASI.CONSTANT_ADDRESS);
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LLT PtrType = getLLTForType(*PtrTy, DL);
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unsigned DstReg = MRI.createGenericVirtualRegister(PtrType);
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unsigned KernArgSegmentPtr =
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TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
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unsigned KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
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unsigned OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(OffsetReg, Offset);
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MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
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return DstReg;
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}
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void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
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Type *ParamTy, unsigned Offset,
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unsigned DstReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUASI.CONSTANT_ADDRESS);
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MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
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unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
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unsigned Align = DL.getABITypeAlignment(ParamTy);
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unsigned PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
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MachineMemOperand::MONonTemporal |
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MachineMemOperand::MOInvariant,
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TypeSize, Align);
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MIRBuilder.buildLoad(DstReg, PtrReg, *MMO);
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}
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bool AMDGPUCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<unsigned> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const SISubtarget *Subtarget = static_cast<const SISubtarget *>(&MF.getSubtarget());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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const SIRegisterInfo *TRI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
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const DataLayout &DL = F.getParent()->getDataLayout();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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// FIXME: How should these inputs interact with inreg / custom SGPR inputs?
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if (Info->hasPrivateSegmentBuffer()) {
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unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
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MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
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CCInfo.AllocateReg(PrivateSegmentBufferReg);
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}
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if (Info->hasDispatchPtr()) {
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unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
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// FIXME: Need to add reg as live-in
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CCInfo.AllocateReg(DispatchPtrReg);
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}
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if (Info->hasQueuePtr()) {
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unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
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// FIXME: Need to add reg as live-in
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CCInfo.AllocateReg(QueuePtrReg);
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}
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if (Info->hasKernargSegmentPtr()) {
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unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
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const LLT P2 = LLT::pointer(2, 64);
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unsigned VReg = MRI.createGenericVirtualRegister(P2);
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MRI.addLiveIn(InputPtrReg, VReg);
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MIRBuilder.getMBB().addLiveIn(InputPtrReg);
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MIRBuilder.buildCopy(VReg, InputPtrReg);
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CCInfo.AllocateReg(InputPtrReg);
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}
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if (Info->hasDispatchID()) {
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unsigned DispatchIDReg = Info->addDispatchID(*TRI);
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// FIXME: Need to add reg as live-in
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CCInfo.AllocateReg(DispatchIDReg);
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}
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if (Info->hasFlatScratchInit()) {
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unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);
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// FIXME: Need to add reg as live-in
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CCInfo.AllocateReg(FlatScratchInitReg);
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}
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unsigned NumArgs = F.arg_size();
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Function::const_arg_iterator CurOrigArg = F.arg_begin();
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const AMDGPUTargetLowering &TLI = *getTLI<AMDGPUTargetLowering>();
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for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) {
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MVT ValVT = TLI.getValueType(DL, CurOrigArg->getType()).getSimpleVT();
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ISD::ArgFlagsTy Flags;
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Flags.setOrigAlign(DL.getABITypeAlignment(CurOrigArg->getType()));
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CCAssignFn *AssignFn = CCAssignFnForCall(F.getCallingConv(),
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/*IsVarArg=*/false);
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bool Res =
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AssignFn(i, ValVT, ValVT, CCValAssign::Full, Flags, CCInfo);
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assert(!Res && "Call operand has unhandled type");
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(void)Res;
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}
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Function::const_arg_iterator Arg = F.arg_begin();
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for (unsigned i = 0; i != NumArgs; ++i, ++Arg) {
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// FIXME: We should be getting DebugInfo from the arguments some how.
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CCValAssign &VA = ArgLocs[i];
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lowerParameter(MIRBuilder, Arg->getType(),
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VA.getLocMemOffset() +
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Subtarget->getExplicitKernelArgOffset(MF), VRegs[i]);
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}
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return true;
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}
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