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llvm-mirror/test/CodeGen
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Craig Topper 558281ef53 [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported. 
Rather than using SELECT instructions, use SRA, UADDO/ADDCARRY and
XORs to expand ABS. This is the multi-part version of the sequence
we use in LegalizeDAG.

It's also the same as the Custom sequence uses for i64 on 32-bit
and i128 on 64-bit. So we can remove the X86 customization.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D87215
2020-09-07 13:15:26 -07:00
..
AArch64 [DAGCombiner] allow more store merging for non-i8 truncated ops 2020-09-07 14:12:36 -04:00
AMDGPU [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block 2020-09-07 19:37:27 +03:00
ARC [ARC] Update brcc test. 2020-08-28 17:07:25 -07:00
ARM Follow up of rG5f1cad4d296a, slightly reduced test case. NFC. 2020-09-07 15:11:10 +01:00
AVR
BPF
Generic
Hexagon [Hexagon] When widening truncate result, also widen operand if necessary 2020-09-05 18:19:32 -05:00
Inputs
Lanai
Mips
MIR [MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo) 2020-09-03 16:13:09 -04:00
MSP430
NVPTX
PowerPC [NFC][PowerPC] Add tests in constants-i64.ll. 2020-09-07 13:14:00 +00:00
RISCV
SPARC [Sparc] Add reduced funnel shift test case for PR47303 2020-09-07 16:17:31 +01:00
SystemZ [SelectionDAG] Always intersect SDNode flags during getNode() node memoization. 2020-09-05 10:30:38 +02:00
Thumb
Thumb2 [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported. 2020-09-07 13:15:26 -07:00
VE
WebAssembly [WebAssembly] Fix incorrect assumption of simple value types 2020-09-06 15:42:21 -07:00
WinCFGuard
WinEH
X86 [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported. 2020-09-07 13:15:26 -07:00
XCore