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3e2b8f42e3
The test case provided in PR45709 can be simplified by DCE to an empty function. To prevent this from happening if DCE is run prior to ISEL in the back end, just add optnone to the function. The behaviour it is testing for is in the SDAG legalization and is not sensitive to optnone so the test case still achieves its desired objective.
66 lines
2.5 KiB
LLVM
66 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr6 -ppc-asm-full-reg-names -mattr=-vsx \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC.
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; On PPC, we had SELECT_CC legalized using Promote for all vector types
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; (including the type that they are all promoted to - which caused an infinite
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; loop in legalization). This test just ensures that we terminate on such input.
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define dso_local void @_ZN1a1bEv(<4 x float> %in) local_unnamed_addr #0 align 2 {
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; CHECK-LABEL: _ZN1a1bEv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_1: # %.preheader
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-NEXT: lvx v3, 0, r3
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; CHECK-NEXT: vperm v2, v2, v2, v3
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; CHECK-NEXT: vxor v3, v3, v3
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; CHECK-NEXT: addi r3, r1, -48
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; CHECK-NEXT: stvx v3, 0, r3
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; CHECK-NEXT: addi r3, r1, -32
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; CHECK-NEXT: stvx v2, 0, r3
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; CHECK-NEXT: lwz r3, -48(r1)
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; CHECK-NEXT: lwz r4, -32(r1)
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; CHECK-NEXT: cmpw r4, r3
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; CHECK-NEXT: bc 12, gt, .LBB0_4
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; CHECK-NEXT: b .LBB0_5
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: addi r3, r4, 0
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: cmpw r3, r3
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; CHECK-NEXT: stw r3, -64(r1)
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; CHECK-NEXT: addi r3, r1, -64
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; CHECK-NEXT: lvx v2, 0, r3
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; CHECK-NEXT: addi r3, r1, -16
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; CHECK-NEXT: stvx v2, 0, r3
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; CHECK-NEXT: .LBB0_6:
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; CHECK-NEXT: blr
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br i1 undef, label %7, label %1
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1: ; preds = %1, %0
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br i1 undef, label %2, label %1
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2: ; preds = %1
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%3 = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
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%4 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %3, <4 x float> zeroinitializer)
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%5 = call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %4, <4 x float> undef)
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%6 = extractelement <4 x float> %5, i32 0
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br label %7
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7: ; preds = %2, %0
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%8 = phi float [ %6, %2 ], [ undef, %0 ]
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%9 = fcmp fast une float %8, 0.000000e+00
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ret void
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}
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declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #0
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attributes #0 = { nounwind optnone noinline }
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