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251919f579
LLVM normally prefers to minimize the number of bits set in an AND immediate, but that doesn't always match the available ARM instructions. In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer a two-instruction sequence movs+ands or movs+bics. Some potential improvements outlined in ARMTargetLowering::targetShrinkDemandedConstant, but seems to work pretty well already. The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX instruction due to a larger-than-expected mask. (It's orthogonal, in some sense, but as far as I can tell it's either impossible or nearly impossible to reproduce the bug without this change.) According to my testing, this seems to consistently improve codesize by a small amount by forming bic more often for ISD::AND with an immediate. Differential Revision: https://reviews.llvm.org/D50030 llvm-svn: 339472
116 lines
3.0 KiB
LLVM
116 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m0 -verify-machineinstrs | FileCheck --check-prefix CHECK-T1 %s
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; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m3 -verify-machineinstrs | FileCheck --check-prefix CHECK-T2 %s
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define i32 @i(i32 %a) {
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; CHECK-T1-LABEL: i:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: movs r1, #255
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; CHECK-T1-NEXT: adds r1, #20
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; CHECK-T1-NEXT: bics r0, r1
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: i:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: movw r1, #275
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; CHECK-T2-NEXT: bics r0, r1
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; CHECK-T2-NEXT: bx lr
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entry:
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%and = and i32 %a, -276
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ret i32 %and
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}
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define i32 @j(i32 %a) {
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; CHECK-T1-LABEL: j:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: movs r1, #128
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; CHECK-T1-NEXT: bics r0, r1
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: j:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: bic r0, r0, #128
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; CHECK-T2-NEXT: bx lr
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entry:
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%and = and i32 %a, -129
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ret i32 %and
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}
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define void @truncated(i16 %a, i16* %p) {
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; CHECK-T1-LABEL: truncated:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: movs r2, #128
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; CHECK-T1-NEXT: bics r0, r2
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; CHECK-T1-NEXT: strh r0, [r1]
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: truncated:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: bic r0, r0, #128
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; CHECK-T2-NEXT: strh r0, [r1]
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; CHECK-T2-NEXT: bx lr
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%and = and i16 %a, -129
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store i16 %and, i16* %p
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ret void
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}
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define void @truncated_neg2(i16 %a, i16* %p) {
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; CHECK-T1-LABEL: truncated_neg2:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: movs r2, #1
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; CHECK-T1-NEXT: bics r0, r2
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; CHECK-T1-NEXT: strh r0, [r1]
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: truncated_neg2:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: bic r0, r0, #1
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; CHECK-T2-NEXT: strh r0, [r1]
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; CHECK-T2-NEXT: bx lr
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%and = and i16 %a, -2
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store i16 %and, i16* %p
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ret void
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}
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define void @truncated_neg256(i16 %a, i16* %p) {
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; CHECK-T1-LABEL: truncated_neg256:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: movs r2, #255
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; CHECK-T1-NEXT: bics r0, r2
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; CHECK-T1-NEXT: strh r0, [r1]
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: truncated_neg256:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: bic r0, r0, #255
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; CHECK-T2-NEXT: strh r0, [r1]
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; CHECK-T2-NEXT: bx lr
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%and = and i16 %a, -256
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store i16 %and, i16* %p
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ret void
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}
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; FIXME: Thumb2 supports "bic r0, r0, #510"
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define void @truncated_neg511(i16 %a, i16* %p) {
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; CHECK-T1-LABEL: truncated_neg511:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: ldr r2, .LCPI5_0
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; CHECK-T1-NEXT: ands r2, r0
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; CHECK-T1-NEXT: strh r2, [r1]
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: .LCPI5_0:
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; CHECK-T1-NEXT: .long 65025 @ 0xfe01
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;
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; CHECK-T2-LABEL: truncated_neg511:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: movw r2, #65025
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; CHECK-T2-NEXT: ands r0, r2
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; CHECK-T2-NEXT: strh r0, [r1]
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; CHECK-T2-NEXT: bx lr
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%and = and i16 %a, -511
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store i16 %and, i16* %p
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ret void
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}
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