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32d4c1b0c4
This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
23 lines
646 B
LLVM
23 lines
646 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+clzero | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i386-pc-linux -mattr=+clzero | FileCheck %s --check-prefix=X32
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define void @foo(i8* %p) #0 {
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; X64-LABEL: foo:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: clzero
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; X64-NEXT: retq
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;
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; X32-LABEL: foo:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: clzero
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; X32-NEXT: retl
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entry:
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tail call void @llvm.x86.clzero(i8* %p) #1
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ret void
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}
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declare void @llvm.x86.clzero(i8*) #1
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