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The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). llvm-svn: 178480
28 lines
977 B
LLVM
28 lines
977 B
LLVM
; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @test(i64 %x) nounwind readnone {
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entry:
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%conv = sitofp i64 %x to float
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ret float %conv
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}
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; Verify that we get the code sequence needed to avoid double-rounding.
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; Note that only parts of the sequence are checked for here, to allow
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; for minor code generation differences.
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; CHECK: sradi [[REG1:[0-9]+]], 3, 53
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; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
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; CHECK: cmpldi 0, [[REG2]], 1
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; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
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; CHECK: std [[REG3]], -{{[0-9]+}}(1)
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; Also check that with -enable-unsafe-fp-math we do not get that extra
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; code sequence. Simply verify that there is no "isel" present.
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; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
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; CHECK-UNSAFE-NOT: isel
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