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0e7935e723
This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual method to perform post-selection peephole optimizations on the DAG representation. One optimization is implemented here: folds to clean up complex addressing expressions for thread-local storage and medium code model. It will also be useful for large code model sequences when those are added later. I originally thought about doing this on the MI representation prior to register assignment, but it's difficult to do effective global dead code elimination at that point. DCE is trivial on the DAG representation. A typical example of a candidate code sequence in assembly: addis 3, 2, globalvar@toc@ha addi 3, 3, globalvar@toc@l lwz 5, 0(3) When the final instruction is a load or store with an immediate offset of zero, the offset from the add-immediate can replace the zero, provided the relocation information is carried along: addis 3, 2, globalvar@toc@ha lwz 5, globalvar@toc@l(3) Since the addi can in general have multiple uses, we need to only delete the instruction when the last use is removed. llvm-svn: 175697
28 lines
863 B
LLVM
28 lines
863 B
LLVM
; RUN: llc -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s
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; Test peephole optimization for medium code model (32-bit TOC offsets)
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; for loading and storing a file-scope static variable.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@gi = global i32 5, align 4
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define signext i32 @test_file_static() nounwind {
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entry:
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%0 = load i32* @gi, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @gi, align 4
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ret i32 %0
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}
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; CHECK: test_file_static:
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; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
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; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
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; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
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; CHECK: .type [[VAR]],@object
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; CHECK: .data
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; CHECK: .globl [[VAR]]
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; CHECK: [[VAR]]:
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; CHECK: .long 5
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