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624f5d5d67
Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. llvm-svn: 174746
48 lines
1.4 KiB
LLVM
48 lines
1.4 KiB
LLVM
; RUN: llc -mcpu=a2 -disable-lsr < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i32 @test1(i64 %add, i64* %ptr) nounwind {
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entry:
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%p1 = getelementptr i64* %ptr, i64 144115188075855
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br label %for.cond2.preheader
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for.cond2.preheader:
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%nl.018 = phi i32 [ 0, %entry ], [ %inc9, %for.end ]
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br label %for.body4
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for.body4:
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%lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
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%i0 = phi i64* [ %p1, %for.cond2.preheader ], [ %i6, %for.body4 ]
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%i6 = getelementptr i64* %i0, i64 400000
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%i7 = getelementptr i64* %i6, i64 300000
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%i8 = getelementptr i64* %i6, i64 200000
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%i9 = getelementptr i64* %i6, i64 100000
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store i64 %add, i64* %i6, align 32
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store i64 %add, i64* %i7, align 32
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store i64 %add, i64* %i8, align 32
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store i64 %add, i64* %i9, align 32
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%lsr.iv.next = add i32 %lsr.iv, -16
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%exitcond.15 = icmp eq i32 %lsr.iv.next, 0
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br i1 %exitcond.15, label %for.end, label %for.body4
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; Make sure that we generate the most compact form of this loop with no
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; unnecessary moves
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; CHECK: @test1
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; CHECK: mtctr
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; CHECK: stdux
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; CHECK-NEXT: stdx
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; CHECK-NEXT: stdx
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; CHECK-NEXT: stdx
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; CHECK-NEXT: bdnz
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for.end:
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%inc9 = add nsw i32 %nl.018, 1
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%exitcond = icmp eq i32 %inc9, 400000
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br i1 %exitcond, label %for.end10, label %for.cond2.preheader
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for.end10:
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ret i32 0
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}
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