Farhana Aleen c0ae8f8658 [AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space. ... Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64. This patch supports ds_read_b128 instruction pattern and generation of this instruction. In the vectorizer, this patch also widen the vector length so that vectorizer generates 128 bit loads for local address-space which gets translated to ds_read_b128. Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128. Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44210 llvm-svn: 327153		2018-03-09 17:41:39 +00:00
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AMDGPU	[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.	2018-03-09 17:41:39 +00:00
NVPTX
X86	[LoadStoreVectorizer] Differentiate between <1 x T> and T	2018-03-07 10:29:28 +00:00
int_sideeffect.ll	Add an @llvm.sideeffect intrinsic	2017-11-08 21:59:51 +00:00