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ee3af15269
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
585 lines
21 KiB
C++
585 lines
21 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "SequenceToOffsetTable.h"
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#include "TableGenBackends.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <algorithm>
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#include <cstdio>
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#include <map>
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#include <vector>
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using namespace llvm;
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namespace {
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class InstrInfoEmitter {
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RecordKeeper &Records;
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CodeGenDAGPatterns CDP;
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const CodeGenSchedModels &SchedModels;
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public:
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InstrInfoEmitter(RecordKeeper &R):
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Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
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// run - Output the instruction set description.
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void run(raw_ostream &OS);
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private:
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void emitEnums(raw_ostream &OS);
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typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
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/// The keys of this map are maps which have OpName enum values as their keys
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/// and instruction operand indices as their values. The values of this map
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/// are lists of instruction names.
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typedef std::map<std::map<unsigned, unsigned>,
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std::vector<std::string> > OpNameMapTy;
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typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS);
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void initOperandMapData(
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const std::vector<const CodeGenInstruction *> NumberedInstructions,
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const std::string &Namespace,
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std::map<std::string, unsigned> &Operands,
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OpNameMapTy &OperandMap);
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void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
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const std::vector<const CodeGenInstruction*> &NumberedInstructions);
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// Operand information.
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void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
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std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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};
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} // End anonymous namespace
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static void PrintDefList(const std::vector<Record*> &Uses,
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unsigned Num, raw_ostream &OS) {
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OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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OS << "0 };\n";
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}
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CGIOperandList::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Inst.Operands[i]);
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} else {
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for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
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OperandList.push_back(Inst.Operands[i]);
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Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterOperand"))
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OpR = OpR->getValueAsDef("RegClass");
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
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else
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// -1 means the operand does not have a fixed register class.
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Res += "-1, ";
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// Fill in applicable flags.
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Res += "0";
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// Ptr value whose register class is resolved via callback.
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if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += "|(1<<MCOI::LookupPtrRegClass)";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOp.
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if (Inst.Operands[i].Rec->isSubClassOf("PredicateOp"))
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Res += "|(1<<MCOI::Predicate)";
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
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Res += "|(1<<MCOI::OptionalDef)";
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// Fill in operand type.
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Res += ", MCOI::";
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assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
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Res += Inst.Operands[i].OperandType;
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// Fill in constraint info.
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Res += ", ";
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const CGIOperandList::ConstraintInfo &Constraint =
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Inst.Operands[i].Constraints[j];
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if (Constraint.isNone())
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Res += "0";
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else if (Constraint.isEarlyClobber())
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Res += "(1 << MCOI::EARLY_CLOBBER)";
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else {
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assert(Constraint.isTied());
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Res += "((" + utostr(Constraint.getTiedOperand()) +
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" << 16) | (1 << MCOI::TIED_TO))";
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}
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Result.push_back(Res);
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}
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}
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return Result;
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}
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<std::string> OperandInfo = GetOperandInfo(**II);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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N = ++OperandListNum;
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OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
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OS << "{ " << OperandInfo[i] << " }, ";
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OS << "};\n";
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}
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}
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/// Initialize data structures for generating operand name mappings.
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///
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/// \param Operands [out] A map used to generate the OpName enum with operand
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/// names as its keys and operand enum values as its values.
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/// \param OperandMap [out] A map for representing the operand name mappings for
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/// each instructions. This is used to generate the OperandMap table as
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/// well as the getNamedOperandIdx() function.
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void InstrInfoEmitter::initOperandMapData(
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const std::vector<const CodeGenInstruction *> NumberedInstructions,
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const std::string &Namespace,
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std::map<std::string, unsigned> &Operands,
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OpNameMapTy &OperandMap) {
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unsigned NumOperands = 0;
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const CodeGenInstruction *Inst = NumberedInstructions[i];
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if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) {
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continue;
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}
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std::map<unsigned, unsigned> OpList;
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for (unsigned j = 0, je = Inst->Operands.size(); j != je; ++j) {
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const CGIOperandList::OperandInfo &Info = Inst->Operands[j];
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StrUintMapIter I = Operands.find(Info.Name);
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if (I == Operands.end()) {
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I = Operands.insert(Operands.begin(),
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std::pair<std::string, unsigned>(Info.Name, NumOperands++));
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}
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OpList[I->second] = Info.MIOperandNo;
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}
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OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName());
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}
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}
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/// Generate a table and function for looking up the indices of operands by
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/// name.
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///
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/// This code generates:
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/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
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/// for each operand name.
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/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
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/// operand indices.
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/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
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/// for looking up the operand index for an instruction, given a value from
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/// OpName enum
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void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
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const CodeGenTarget &Target,
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const std::vector<const CodeGenInstruction*> &NumberedInstructions) {
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const std::string &Namespace = Target.getInstNamespace();
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std::string OpNameNS = "OpName";
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// Map of operand names to their enumeration value. This will be used to
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// generate the OpName enum.
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std::map<std::string, unsigned> Operands;
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OpNameMapTy OperandMap;
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initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
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OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
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OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
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OS << "namespace llvm {";
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OS << "namespace " << Namespace << " {\n";
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OS << "namespace " << OpNameNS << " { \n";
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OS << "enum {\n";
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for (StrUintMapIter i = Operands.begin(), e = Operands.end(); i != e; ++i)
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OS << " " << i->first << " = " << i->second << ",\n";
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OS << "OPERAND_LAST";
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OS << "\n};\n";
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OS << "} // End namespace OpName\n";
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OS << "} // End namespace " << Namespace << "\n";
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OS << "} // End namespace llvm\n";
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OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n";
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OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
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OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
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OS << "namespace llvm {";
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OS << "namespace " << Namespace << " {\n";
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OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
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if (!Operands.empty()) {
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OS << " static const int16_t OperandMap [][" << Operands.size()
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<< "] = {\n";
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for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end();
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i != e; ++i) {
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const std::map<unsigned, unsigned> &OpList = i->first;
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OS << "{";
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// Emit a row of the OperandMap table
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for (unsigned ii = 0, ie = Operands.size(); ii != ie; ++ii)
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OS << (OpList.count(ii) == 0 ? -1 : (int)OpList.find(ii)->second)
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<< ", ";
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OS << "},\n";
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}
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OS << "};\n";
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OS << " switch(Opcode) {\n";
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unsigned TableIndex = 0;
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for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end();
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i != e; ++i) {
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std::vector<std::string> &OpcodeList = i->second;
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for (unsigned ii = 0, ie = OpcodeList.size(); ii != ie; ++ii)
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OS << " case " << OpcodeList[ii] << ":\n";
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OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
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}
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OS << " default: return -1;\n";
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OS << " }\n";
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} else {
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// There are no operands, so no need to emit anything
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OS << " return -1;\n";
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}
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OS << "}\n";
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OS << "} // End namespace " << Namespace << "\n";
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OS << "} // End namespace llvm\n";
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OS << "#endif //GET_INSTRINFO_NAMED_OPS\n";
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(raw_ostream &OS) {
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emitSourceFileHeader("Target Instruction Enum Values", OS);
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emitEnums(OS);
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emitSourceFileHeader("Target Instruction Descriptors", OS);
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OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
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OS << "#undef GET_INSTRINFO_MC_DESC\n";
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OS << "namespace llvm {\n\n";
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CodeGenTarget &Target = CDP.getTargetInfo();
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = (*II)->TheDef;
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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unsigned &IL = EmittedLists[Uses];
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if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
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}
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std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
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if (!Defs.empty()) {
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unsigned &IL = EmittedLists[Defs];
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if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
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}
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}
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OperandInfoMapTy OperandInfoIDs;
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// Emit all of the operand info records.
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EmitOperandInfo(OS, OperandInfoIDs);
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// Emit all of the MCInstrDesc records in their ENUM ordering.
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//
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OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
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const std::vector<const CodeGenInstruction*> &NumberedInstructions =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
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emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
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OperandInfoIDs, OS);
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OS << "};\n\n";
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// Build an array of instruction names
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SequenceToOffsetTable<std::string> InstrNames;
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const CodeGenInstruction *Instr = NumberedInstructions[i];
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InstrNames.add(Instr->TheDef->getName());
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}
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InstrNames.layout();
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OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
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InstrNames.emit(OS, printChar);
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OS << "};\n\n";
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OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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if (i % 8 == 0)
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OS << "\n ";
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const CodeGenInstruction *Instr = NumberedInstructions[i];
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OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
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}
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OS << "\n};\n\n";
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// MCInstrInfo initialization routine.
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OS << "static inline void Init" << TargetName
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<< "MCInstrInfo(MCInstrInfo *II) {\n";
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OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
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<< TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
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<< NumberedInstructions.size() << ");\n}\n\n";
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
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// Create a TargetInstrInfo subclass to hide the MC layer initialization.
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OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
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OS << "#undef GET_INSTRINFO_HEADER\n";
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std::string ClassName = TargetName + "GenInstrInfo";
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OS << "namespace llvm {\n";
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OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
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<< " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
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<< " virtual ~" << ClassName << "();\n"
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<< "};\n";
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_INSTRINFO_HEADER\n\n";
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OS << "\n#ifdef GET_INSTRINFO_CTOR_DTOR\n";
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OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
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OS << "namespace llvm {\n";
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OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
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OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
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OS << "extern const char " << TargetName << "InstrNameData[];\n";
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OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
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<< " : TargetInstrInfo(SO, DO) {\n"
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<< " InitMCInstrInfo(" << TargetName << "Insts, "
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<< TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
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<< NumberedInstructions.size() << ");\n}\n"
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<< ClassName << "::~" << ClassName << "() {}\n";
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
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emitOperandNameMappings(OS, Target, NumberedInstructions);
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}
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS) {
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int MinOperands = 0;
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if (!Inst.Operands.empty())
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// Each logical operand can be multiple MI operands.
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MinOperands = Inst.Operands.back().MIOperandNo +
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Inst.Operands.back().MINumOperands;
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OS << " { ";
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OS << Num << ",\t" << MinOperands << ",\t"
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<< Inst.Operands.NumDefs << ",\t"
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<< SchedModels.getSchedClassIdx(Inst) << ",\t"
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<< Inst.TheDef->getValueAsInt("Size") << ",\t0";
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// Emit all of the target indepedent flags...
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if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
|
|
if (Inst.isReturn) OS << "|(1<<MCID::Return)";
|
|
if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
|
|
if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
|
|
if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
|
|
if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
|
|
if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
|
|
if (Inst.isSelect) OS << "|(1<<MCID::Select)";
|
|
if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
|
|
if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
|
|
if (Inst.isCall) OS << "|(1<<MCID::Call)";
|
|
if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
|
|
if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
|
|
if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
|
|
if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
|
|
if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
|
|
if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
|
|
if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
|
|
if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
|
|
if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
|
|
if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
|
|
if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
|
|
if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
|
|
if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
|
|
if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
|
|
if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
|
|
if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
|
|
if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
|
|
|
|
// Emit all of the target-specific flags...
|
|
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
|
|
if (!TSF)
|
|
PrintFatalError("no TSFlags?");
|
|
uint64_t Value = 0;
|
|
for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
|
|
if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
|
|
Value |= uint64_t(Bit->getValue()) << i;
|
|
else
|
|
PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
|
|
}
|
|
OS << ", 0x";
|
|
OS.write_hex(Value);
|
|
OS << "ULL, ";
|
|
|
|
// Emit the implicit uses and defs lists...
|
|
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
|
|
if (UseList.empty())
|
|
OS << "NULL, ";
|
|
else
|
|
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
|
|
|
|
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
|
if (DefList.empty())
|
|
OS << "NULL, ";
|
|
else
|
|
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
|
|
|
|
// Emit the operand info.
|
|
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
|
|
if (OperandInfo.empty())
|
|
OS << "0";
|
|
else
|
|
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
|
|
|
CodeGenTarget &Target = CDP.getTargetInfo();
|
|
if (Inst.HasComplexDeprecationPredicate)
|
|
// Emit a function pointer to the complex predicate method.
|
|
OS << ",0"
|
|
<< ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
|
|
else if (!Inst.DeprecatedReason.empty())
|
|
// Emit the Subtarget feature.
|
|
OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
|
|
<< ",0";
|
|
else
|
|
// Instruction isn't deprecated.
|
|
OS << ",0,0";
|
|
|
|
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
|
}
|
|
|
|
// emitEnums - Print out enum values for all of the instructions.
|
|
void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
|
|
|
|
OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
|
|
OS << "#undef GET_INSTRINFO_ENUM\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
CodeGenTarget Target(Records);
|
|
|
|
// We must emit the PHI opcode first...
|
|
std::string Namespace = Target.getInstNamespace();
|
|
|
|
if (Namespace.empty()) {
|
|
fprintf(stderr, "No instructions defined!\n");
|
|
exit(1);
|
|
}
|
|
|
|
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
|
|
Target.getInstructionsByEnumValue();
|
|
|
|
OS << "namespace " << Namespace << " {\n";
|
|
OS << " enum {\n";
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
OS << " " << NumberedInstructions[i]->TheDef->getName()
|
|
<< "\t= " << i << ",\n";
|
|
}
|
|
OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
|
|
OS << " };\n";
|
|
OS << "namespace Sched {\n";
|
|
OS << " enum {\n";
|
|
for (unsigned i = 0, e = SchedModels.numInstrSchedClasses(); i != e; ++i) {
|
|
OS << " " << SchedModels.getSchedClass(i).Name
|
|
<< "\t= " << i << ",\n";
|
|
}
|
|
OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n";
|
|
OS << " };\n}\n}\n";
|
|
OS << "} // End llvm namespace \n";
|
|
|
|
OS << "#endif // GET_INSTRINFO_ENUM\n\n";
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
|
|
InstrInfoEmitter(RK).run(OS);
|
|
EmitMapTable(RK, OS);
|
|
}
|
|
|
|
} // End llvm namespace
|