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122 lines
3.8 KiB
C++
122 lines
3.8 KiB
C++
//===- NVPTXProxyRegErasure.cpp - NVPTX Proxy Register Instruction Erasure -==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The pass is needed to remove ProxyReg instructions and restore related
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// registers. The instructions were needed at instruction selection stage to
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// make sure that callseq_end nodes won't be removed as "dead nodes". This can
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// happen when we expand instructions into libcalls and the call site doesn't
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// care about the libcall chain. Call site cares about data flow only, and the
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// latest data flow node happens to be before callseq_end. Therefore the node
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// becomes dangling and "dead". The ProxyReg acts like an additional data flow
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// node *after* the callseq_end in the chain and ensures that everything will be
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// preserved.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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namespace llvm {
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void initializeNVPTXProxyRegErasurePass(PassRegistry &);
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}
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namespace {
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struct NVPTXProxyRegErasure : public MachineFunctionPass {
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public:
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static char ID;
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NVPTXProxyRegErasure() : MachineFunctionPass(ID) {
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initializeNVPTXProxyRegErasurePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "NVPTX Proxy Register Instruction Erasure";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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void replaceMachineInstructionUsage(MachineFunction &MF, MachineInstr &MI);
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void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
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MachineOperand &To);
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};
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} // namespace
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char NVPTXProxyRegErasure::ID = 0;
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INITIALIZE_PASS(NVPTXProxyRegErasure, "nvptx-proxyreg-erasure", "NVPTX ProxyReg Erasure", false, false)
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bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
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SmallVector<MachineInstr *, 16> RemoveList;
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for (auto &BB : MF) {
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for (auto &MI : BB) {
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switch (MI.getOpcode()) {
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case NVPTX::ProxyRegI1:
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case NVPTX::ProxyRegI16:
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case NVPTX::ProxyRegI32:
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case NVPTX::ProxyRegI64:
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case NVPTX::ProxyRegF16:
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case NVPTX::ProxyRegF16x2:
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case NVPTX::ProxyRegF32:
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case NVPTX::ProxyRegF64:
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replaceMachineInstructionUsage(MF, MI);
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RemoveList.push_back(&MI);
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break;
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}
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}
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}
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for (auto *MI : RemoveList) {
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MI->eraseFromParent();
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}
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return !RemoveList.empty();
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}
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void NVPTXProxyRegErasure::replaceMachineInstructionUsage(MachineFunction &MF,
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MachineInstr &MI) {
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auto &InOp = *MI.uses().begin();
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auto &OutOp = *MI.defs().begin();
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assert(InOp.isReg() && "ProxyReg input operand should be a register.");
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assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
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for (auto &BB : MF) {
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for (auto &I : BB) {
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replaceRegisterUsage(I, OutOp, InOp);
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}
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}
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}
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void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr,
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MachineOperand &From,
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MachineOperand &To) {
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for (auto &Op : Instr.uses()) {
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if (Op.isReg() && Op.getReg() == From.getReg()) {
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Op.setReg(To.getReg());
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}
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}
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}
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MachineFunctionPass *llvm::createNVPTXProxyRegErasurePass() {
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return new NVPTXProxyRegErasure();
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}
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