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ce7b184512
- Handle simple cases of register copies (what current RDF CP allows). - Hexagon-specific dead code elimination: handles dead address updates in post-increment instructions. llvm-svn: 257504
61 lines
1.7 KiB
C++
61 lines
1.7 KiB
C++
//===--- HexagonRDF.cpp ---------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonRDF.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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using namespace llvm;
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using namespace rdf;
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bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const {
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if (RA == RB)
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return true;
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if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
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TargetRegisterInfo::isVirtualRegister(RB.Reg)) {
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// Hexagon-specific cases.
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if (RA.Reg == RB.Reg) {
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if (RA.Sub == 0)
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return true;
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if (RB.Sub == 0)
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return false;
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}
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}
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return RegisterAliasInfo::covers(RA, RB);
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}
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bool HexagonRegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR)
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const {
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if (RRs.count(RR))
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return true;
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if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) {
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assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
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// Check if both covering subregisters are present.
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bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg});
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bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg});
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if (HasLo && HasHi)
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return true;
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}
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if (RR.Sub == 0) {
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// Check if both covering subregisters are present.
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unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg);
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unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg);
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if (RRs.count({Lo, 0}) && RRs.count({Hi, 0}))
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return true;
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}
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return RegisterAliasInfo::covers(RRs, RR);
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}
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