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65b09f0c51
This patch fixes a very subtle bug in regmask calculation. Thanks to zan jyu Wong <zyfwong@gmail.com> for bringing this to notice. For example if CL is only clobbered than CH should not be marked clobbered but CX, RCX and ECX should be mark clobbered. Previously for each modified register all of its aliases are marked clobbered by markRegClobbred() in RegUsageInfoCollector.cpp but that is wrong because when CL is clobbered then MRI::isPhysRegModified() will return true for CL, CX, ECX, RCX which is correct behavior but then for CX, EXC, RCX we mark CH also clobbered as CH is aliased to CX,ECX,RCX so markRegClobbred() is not required because isPhysRegModified already take cares of proper aliasing register. A very simple test case has been added to verify this change. Please find relevant bug report here : http://llvm.org/PR28567 Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: https://reviews.llvm.org/D22400 llvm-svn: 276235
132 lines
4.5 KiB
C++
132 lines
4.5 KiB
C++
//===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// This pass is required to take advantage of the interprocedural register
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/// allocation infrastructure.
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///
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/// This pass is simple MachineFunction pass which collects register usage
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/// details by iterating through each physical registers and checking
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/// MRI::isPhysRegUsed() then creates a RegMask based on this details.
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/// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterUsageInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "ip-regalloc"
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STATISTIC(NumCSROpt,
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"Number of functions optimized for callee saved registers");
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namespace llvm {
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void initializeRegUsageInfoCollectorPass(PassRegistry &);
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}
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namespace {
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class RegUsageInfoCollector : public MachineFunctionPass {
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public:
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RegUsageInfoCollector() : MachineFunctionPass(ID) {
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PassRegistry &Registry = *PassRegistry::getPassRegistry();
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initializeRegUsageInfoCollectorPass(Registry);
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}
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const char *getPassName() const override {
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return "Register Usage Information Collector Pass";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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static char ID;
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};
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} // end of anonymous namespace
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char RegUsageInfoCollector::ID = 0;
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INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
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"Register Usage Information Collector", false, false)
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INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
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INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
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"Register Usage Information Collector", false, false)
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FunctionPass *llvm::createRegUsageInfoCollector() {
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return new RegUsageInfoCollector();
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}
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void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<PhysicalRegisterUsageInfo>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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const TargetMachine &TM = MF.getTarget();
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DEBUG(dbgs() << " -------------------- " << getPassName()
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<< " -------------------- \n");
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DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
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std::vector<uint32_t> RegMask;
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// Compute the size of the bit vector to represent all the registers.
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// The bit vector is broken into 32-bit chunks, thus takes the ceil of
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// the number of registers divided by 32 for the size.
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unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
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RegMask.resize(RegMaskSize, 0xFFFFFFFF);
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const Function *F = MF.getFunction();
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PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
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PRUI->setTargetMachine(&TM);
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DEBUG(dbgs() << "Clobbered Registers: ");
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
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if (MRI->isPhysRegModified(PReg, true))
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RegMask[PReg / 32] &= ~(1u << PReg % 32);
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if (!TargetFrameLowering::isSafeForNoCSROpt(F)) {
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const uint32_t *CallPreservedMask =
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TRI->getCallPreservedMask(MF, F->getCallingConv());
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// Set callee saved register as preserved.
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for (unsigned i = 0; i < RegMaskSize; ++i)
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RegMask[i] = RegMask[i] | CallPreservedMask[i];
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} else {
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++NumCSROpt;
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DEBUG(dbgs() << MF.getName()
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<< " function optimized for not having CSR.\n");
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}
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
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if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
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DEBUG(dbgs() << TRI->getName(PReg) << " ");
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DEBUG(dbgs() << " \n----------------------------------------\n");
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PRUI->storeUpdateRegUsageInfo(F, std::move(RegMask));
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return false;
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}
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