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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
101 lines
3.4 KiB
C++
101 lines
3.4 KiB
C++
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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const TargetRegisterInfo &TRI) {
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// FIXME: Detect integer instructions properly.
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const MCInstrDesc &MCID = MI->getDesc();
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unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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if (MI->mayStore())
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return false;
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unsigned Opcode = MCID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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return false;
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugInstr()) {
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// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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// a VMLA / VMLS will cause 4 cycle stall.
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const MCInstrDesc &MCID = MI->getDesc();
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if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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MachineInstr *DefMI = LastMI;
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const MCInstrDesc &LastMCID = LastMI->getDesc();
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const MachineFunction *MF = MI->getParent()->getParent();
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const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
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MF->getSubtarget().getInstrInfo());
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// Skip over one non-VFP / NEON instruction.
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if (!LastMI->isBarrier() &&
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!(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
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(LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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MachineBasicBlock::iterator I = LastMI;
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if (I != LastMI->getParent()->begin()) {
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I = std::prev(I);
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DefMI = &*I;
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}
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}
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if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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(TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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// Try to schedule another instruction for the next 4 cycles.
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if (FpMLxStalls == 0)
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FpMLxStalls = 4;
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return Hazard;
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}
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}
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}
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void ARMHazardRecognizer::Reset() {
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LastMI = nullptr;
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FpMLxStalls = 0;
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ScoreboardHazardRecognizer::Reset();
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}
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void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugInstr()) {
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LastMI = MI;
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FpMLxStalls = 0;
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}
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ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void ARMHazardRecognizer::AdvanceCycle() {
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if (FpMLxStalls && --FpMLxStalls == 0)
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// Stalled for 4 cycles but still can't schedule any other instructions.
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LastMI = nullptr;
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ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void ARMHazardRecognizer::RecedeCycle() {
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llvm_unreachable("reverse ARM hazard checking unsupported");
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}
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