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2d2e4a1b17
I have added a new FastMathFlags parameter to getArithmeticReductionCost to indicate what type of reduction we are performing: 1. Tree-wise. This is the typical fast-math reduction that involves continually splitting a vector up into halves and adding each half together until we get a scalar result. This is the default behaviour for integers, whereas for floating point we only do this if reassociation is allowed. 2. Ordered. This now allows us to estimate the cost of performing a strict vector reduction by treating it as a series of scalar operations in lane order. This is the case when FP reassociation is not permitted. For scalable vectors this is more difficult because at compile time we do not know how many lanes there are, and so we use the worst case maximum vscale value. I have also fixed getTypeBasedIntrinsicInstrCost to pass in the FastMathFlags, which meant fixing up some X86 tests where we always assumed the vector.reduce.fadd/mul intrinsics were 'fast'. New tests have been added here: Analysis/CostModel/AArch64/reduce-fadd.ll Analysis/CostModel/AArch64/sve-intrinsics.ll Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll Differential Revision: https://reviews.llvm.org/D105432
266 lines
11 KiB
C++
266 lines
11 KiB
C++
//===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AMDGPU target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class AMDGPUTargetLowering;
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class AMDGPUTargetMachine;
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class GCNSubtarget;
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class InstCombiner;
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class Loop;
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class R600Subtarget;
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class ScalarEvolution;
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class SITargetLowering;
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class Type;
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class Value;
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class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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using BaseT = BasicTTIImplBase<AMDGPUTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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Triple TargetTriple;
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const TargetSubtargetInfo *ST;
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const TargetLoweringBase *TLI;
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const TargetSubtargetInfo *getST() const { return ST; }
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const TargetLoweringBase *getTLI() const { return TLI; }
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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};
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class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
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using BaseT = BasicTTIImplBase<GCNTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const GCNSubtarget *ST;
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const SITargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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bool IsGraphics;
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bool HasFP32Denormals;
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bool HasFP64FP16Denormals;
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unsigned MaxVGPRs;
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static const FeatureBitset InlineFeatureIgnoreList;
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const GCNSubtarget *getST() const { return ST; }
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const SITargetLowering *getTLI() const { return TLI; }
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static inline int getFullRateInstrCost() {
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return TargetTransformInfo::TCC_Basic;
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}
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static inline int getHalfRateInstrCost(
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) {
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return CostKind == TTI::TCK_CodeSize ? 2
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: 2 * TargetTransformInfo::TCC_Basic;
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}
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// TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
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// should be 2 or 4.
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static inline int getQuarterRateInstrCost(
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) {
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return CostKind == TTI::TCK_CodeSize ? 2
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: 4 * TargetTransformInfo::TCC_Basic;
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}
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// On some parts, normal fp64 operations are half rate, and others
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// quarter. This also applies to some integer operations.
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int get64BitInstrCost(
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
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public:
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explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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bool hasBranchDivergence() { return true; }
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bool useGPUDivergenceAnalysis() const;
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TTI::PSK_FastHardware;
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}
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unsigned getHardwareNumberOfRegisters(bool Vector) const;
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unsigned getNumberOfRegisters(bool Vector) const;
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unsigned getNumberOfRegisters(unsigned RCID) const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
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unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
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unsigned SrcAddrSpace, unsigned DestAddrSpace,
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unsigned SrcAlign, unsigned DestAlign) const;
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void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
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LLVMContext &Context,
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unsigned RemainingBytes,
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unsigned SrcAddrSpace,
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unsigned DestAddrSpace,
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unsigned SrcAlign,
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unsigned DestAlign) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
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InstructionCost getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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bool isInlineAsmSourceOfDivergence(const CallInst *CI,
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ArrayRef<unsigned> Indices = {}) const;
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index);
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bool isSourceOfDivergence(const Value *V) const;
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bool isAlwaysUniform(const Value *V) const;
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unsigned getFlatAddressSpace() const {
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// Don't bother running InferAddressSpaces pass on graphics shaders which
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// don't use flat addressing.
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if (IsGraphics)
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return -1;
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return AMDGPUAS::FLAT_ADDRESS;
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}
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bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
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Intrinsic::ID IID) const;
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Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
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Value *NewV) const;
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bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
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InstCombiner &IC) const;
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Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const;
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Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const;
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InstructionCost getVectorSplitCost() { return 0; }
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask, int Index,
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VectorType *SubTp);
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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unsigned getInliningThresholdMultiplier() { return 11; }
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unsigned adjustInliningThreshold(const CallBase *CB) const;
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int getInlinerVectorBonusPercent() { return 0; }
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InstructionCost getArithmeticReductionCost(
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unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
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InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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InstructionCost getMinMaxReductionCost(
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VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
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};
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class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
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using BaseT = BasicTTIImplBase<R600TTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const R600Subtarget *ST;
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const AMDGPUTargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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public:
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explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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const R600Subtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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unsigned getHardwareNumberOfRegisters(bool Vec) const;
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unsigned getNumberOfRegisters(bool Vec) const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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