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8b2d2affc5
Allow MIMG instructions to be selected with 6/7 VGPRs for vaddr. Previously these were rounded up to VReg_256 this saves VGPRs. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D103800
1142 lines
51 KiB
TableGen
1142 lines
51 KiB
TableGen
//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// MIMG-specific encoding families to distinguish between semantically
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// equivalent machine instructions with different encoding.
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//
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// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8)
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// - MIMGEncGfx8: encoding introduced with gfx8 for atomics
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// - MIMGEncGfx90a: encoding for gfx90a for atomics
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// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding
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// - MIMGEncGfx10NSA: gfx10 NSA encoding
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class MIMGEncoding;
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def MIMGEncGfx6 : MIMGEncoding;
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def MIMGEncGfx8 : MIMGEncoding;
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def MIMGEncGfx90a : MIMGEncoding;
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def MIMGEncGfx10Default : MIMGEncoding;
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def MIMGEncGfx10NSA : MIMGEncoding;
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def MIMGEncoding : GenericEnum {
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let FilterClass = "MIMGEncoding";
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}
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// Represent an ISA-level opcode, independent of the encoding and the
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// vdata/vaddr size.
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class MIMGBaseOpcode : PredicateControl {
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MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
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bit Store = 0;
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bit Atomic = 0;
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bit AtomicX2 = 0; // (f)cmpswap
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bit Sampler = 0;
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bit Gather4 = 0;
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bits<8> NumExtraArgs = 0;
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bit Gradients = 0;
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bit G16 = 0;
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bit Coordinates = 1;
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bit LodOrClampOrMip = 0;
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bit HasD16 = 0;
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bit IsAtomicRet = 0;
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bit MSAA = 0;
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}
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def MIMGBaseOpcode : GenericEnum {
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let FilterClass = "MIMGBaseOpcode";
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}
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def MIMGBaseOpcodesTable : GenericTable {
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let FilterClass = "MIMGBaseOpcode";
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let CppTypeName = "MIMGBaseOpcodeInfo";
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let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
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"Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates",
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"LodOrClampOrMip", "HasD16", "MSAA"];
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string TypeOf_BaseOpcode = "MIMGBaseOpcode";
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let PrimaryKey = ["BaseOpcode"];
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let PrimaryKeyName = "getMIMGBaseOpcodeInfo";
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}
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def MIMGDim : GenericEnum {
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let FilterClass = "AMDGPUDimProps";
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}
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def MIMGDimInfoTable : GenericTable {
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let FilterClass = "AMDGPUDimProps";
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let CppTypeName = "MIMGDimInfo";
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let Fields = ["Dim", "NumCoords", "NumGradients", "MSAA", "DA", "Encoding", "AsmSuffix"];
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string TypeOf_Dim = "MIMGDim";
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let PrimaryKey = ["Dim"];
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let PrimaryKeyName = "getMIMGDimInfo";
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}
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def getMIMGDimInfoByEncoding : SearchIndex {
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let Table = MIMGDimInfoTable;
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let Key = ["Encoding"];
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}
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def getMIMGDimInfoByAsmSuffix : SearchIndex {
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let Table = MIMGDimInfoTable;
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let Key = ["AsmSuffix"];
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}
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def MIMG {
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int NOP = -1;
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}
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class mimgopc <int base, int vi = base, int si = base> {
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field bits<8> BASE = base; // Opcode for all but atomics
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field bits<8> VI = vi; // VI is only used for atomic instructions
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field bits<8> SI = si; // SI is only used for atomic instructions
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bit HAS_BASE = !ne(base, MIMG.NOP);
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bit HAS_VI = !ne(vi, MIMG.NOP);
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bit HAS_SI = !ne(si, MIMG.NOP);
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}
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class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> {
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MIMGBaseOpcode L = l;
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MIMGBaseOpcode LZ = lz;
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}
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def MIMGLZMappingTable : GenericTable {
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let FilterClass = "MIMGLZMapping";
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let CppTypeName = "MIMGLZMappingInfo";
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let Fields = ["L", "LZ"];
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string TypeOf_L = "MIMGBaseOpcode";
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string TypeOf_LZ = "MIMGBaseOpcode";
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let PrimaryKey = ["L"];
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let PrimaryKeyName = "getMIMGLZMappingInfo";
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}
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class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> {
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MIMGBaseOpcode MIP = mip;
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MIMGBaseOpcode NONMIP = nonmip;
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}
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def MIMGMIPMappingTable : GenericTable {
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let FilterClass = "MIMGMIPMapping";
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let CppTypeName = "MIMGMIPMappingInfo";
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let Fields = ["MIP", "NONMIP"];
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string TypeOf_MIP = "MIMGBaseOpcode";
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string TypeOf_NONMIP = "MIMGBaseOpcode";
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let PrimaryKey = ["MIP"];
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let PrimaryKeyName = "getMIMGMIPMappingInfo";
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}
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class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> {
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MIMGBaseOpcode G = g;
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MIMGBaseOpcode G16 = g16;
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}
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def MIMGG16MappingTable : GenericTable {
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let FilterClass = "MIMGG16Mapping";
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let CppTypeName = "MIMGG16MappingInfo";
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let Fields = ["G", "G16"];
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string TypeOf_G = "MIMGBaseOpcode";
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string TypeOf_G16 = "MIMGBaseOpcode";
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let PrimaryKey = ["G"];
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let PrimaryKeyName = "getMIMGG16MappingInfo";
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}
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class MIMG_Base <dag outs, string dns = "">
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: InstSI <outs, (ins), "", []> {
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let MIMG = 1;
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let Uses = [EXEC];
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let mayLoad = 1;
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let mayStore = 0;
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let SchedRW = [WriteVMEM];
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0; // XXX ????
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let DecoderNamespace = dns;
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let isAsmParserOnly = !eq(dns, "");
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}
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class MIMG <dag outs, string dns = "">
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: MIMG_Base <outs, dns> {
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let hasPostISelHook = 1;
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let AsmMatchConverter = "cvtMIMG";
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Instruction Opcode = !cast<Instruction>(NAME);
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MIMGBaseOpcode BaseOpcode;
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MIMGEncoding MIMGEncoding;
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bits<8> VDataDwords;
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bits<8> VAddrDwords;
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}
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def MIMGInfoTable : GenericTable {
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let FilterClass = "MIMG";
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let CppTypeName = "MIMGInfo";
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let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
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string TypeOf_BaseOpcode = "MIMGBaseOpcode";
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string TypeOf_MIMGEncoding = "MIMGEncoding";
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let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
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let PrimaryKeyName = "getMIMGOpcodeHelper";
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}
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def getMIMGInfo : SearchIndex {
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let Table = MIMGInfoTable;
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let Key = ["Opcode"];
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}
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// This class used to use !foldl to memoize the AddrAsmNames list.
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// It turned out that that was much slower than using !filter.
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class MIMGNSAHelper<int num_addrs> {
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list<string> AddrAsmNames =
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!foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11],
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!lt(i, num_addrs)), "vaddr" # i);
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dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames);
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string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]";
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int NSA = !if(!le(num_addrs, 1), ?,
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!if(!le(num_addrs, 5), 1,
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!if(!le(num_addrs, 9), 2,
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!if(!le(num_addrs, 13), 3, ?))));
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}
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// Base class of all pre-gfx10 MIMG instructions.
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class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
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: MIMG<outs, dns>, MIMGe_gfx6789<op> {
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9NotGFX90A;
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let AssemblerPredicate = isGFX6GFX7GFX8GFX9NotGFX90A;
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let MIMGEncoding = MIMGEncGfx6;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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}
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class MIMG_gfx90a<bits<8> op, dag outs, string dns = "">
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: MIMG<outs, dns>, MIMGe_gfx90a<op> {
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let SubtargetPredicate = isGFX90APlus;
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let AssemblerPredicate = isGFX90APlus;
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let MIMGEncoding = MIMGEncGfx90a;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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}
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// Base class of all non-NSA gfx10 MIMG instructions.
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class MIMG_gfx10<int op, dag outs, string dns = "">
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: MIMG<outs, dns>, MIMGe_gfx10<op> {
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let SubtargetPredicate = isGFX10Plus;
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let AssemblerPredicate = isGFX10Plus;
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let MIMGEncoding = MIMGEncGfx10Default;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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let nsa = 0;
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}
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// Base class for all NSA MIMG instructions.
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// Note that 1-dword addresses always use non-NSA variants.
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class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns="">
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: MIMG<outs, dns>, MIMGe_gfx10<op> {
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let SubtargetPredicate = isGFX10Plus;
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let AssemblerPredicate = isGFX10Plus;
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let MIMGEncoding = MIMGEncGfx10NSA;
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MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>;
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dag AddrIns = nsah.AddrIns;
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string AddrAsm = nsah.AddrAsm;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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let nsa = nsah.NSA;
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}
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class MIMG_NoSampler_Helper <mimgopc op, string asm,
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RegisterClass dst_rc,
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RegisterClass addr_rc,
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string dns="">
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: MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> {
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let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
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RegisterClass dst_rc,
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RegisterClass addr_rc,
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string dns="">
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: MIMG_gfx90a <op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
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let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
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RegisterClass DataRC, RegisterClass AddrRC,
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string dns="">
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: MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> {
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let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
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Dim:$dim, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
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RegisterClass DataRC, int num_addrs,
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string dns="">
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: MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> {
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let InOperandList = !con(AddrIns,
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(ins SReg_256:$srsrc, DMask:$dmask,
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Dim:$dim, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
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RegisterClass dst_rc,
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bit enableDisasm,
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bit ExtendedImageInst = 1> {
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let ssamp = 0 in {
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let VAddrDwords = 1 in {
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if op.HAS_BASE then {
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def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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if !not(ExtendedImageInst) then
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def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
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!if(enableDisasm, "GFX90A", "")>;
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def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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}
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let VAddrDwords = 2 in {
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if op.HAS_BASE then {
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def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
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if !not(ExtendedImageInst) then
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def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>;
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def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
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def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
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}
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}
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let VAddrDwords = 3 in {
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if op.HAS_BASE then {
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def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
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if !not(ExtendedImageInst) then
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def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>;
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def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
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def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
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}
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}
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let VAddrDwords = 4 in {
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if op.HAS_BASE then {
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def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
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if !not(ExtendedImageInst) then
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def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>;
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def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
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def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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}
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}
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}
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multiclass MIMG_NoSampler <mimgopc op, string asm, bit has_d16, bit mip = 0,
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bit isResInfo = 0,
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bit msaa = 0> {
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def "" : MIMGBaseOpcode {
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let Coordinates = !not(isResInfo);
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let LodOrClampOrMip = mip;
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let HasD16 = has_d16;
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let MSAA = msaa;
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}
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let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
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mayLoad = !not(isResInfo) in {
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let VDataDwords = 1 in
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defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1, msaa>;
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let VDataDwords = 2 in
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defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0, msaa>;
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let VDataDwords = 3 in
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defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0, msaa>;
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let VDataDwords = 4 in
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defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0, msaa>;
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let VDataDwords = 5 in
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defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0, msaa>;
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}
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}
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class MIMG_Store_Helper <mimgopc op, string asm,
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RegisterClass data_rc,
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RegisterClass addr_rc,
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string dns = "">
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: MIMG_gfx6789<op.BASE, (outs), dns> {
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let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_Store_Helper_gfx90a <mimgopc op, string asm,
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RegisterClass data_rc,
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RegisterClass addr_rc,
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string dns = "">
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: MIMG_gfx90a<op.BASE, (outs), dns> {
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let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata,
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addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, LWE:$lwe, DA:$da),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Store_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, RegisterClass AddrRC,
|
|
string dns="">
|
|
: MIMG_gfx10<op.BASE, (outs), dns> {
|
|
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
|
|
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Store_nsa_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, int num_addrs,
|
|
string dns="">
|
|
: MIMG_nsa_gfx10<op.BASE, (outs), num_addrs, dns> {
|
|
let InOperandList = !con((ins DataRC:$vdata),
|
|
AddrIns,
|
|
(ins SReg_256:$srsrc, DMask:$dmask,
|
|
Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
|
|
RegisterClass data_rc,
|
|
bit enableDisasm> {
|
|
let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0,
|
|
DisableWQM = 1, ssamp = 0 in {
|
|
let VAddrDwords = 1 in {
|
|
if op.HAS_BASE then {
|
|
def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
|
|
!if(enableDisasm, "AMDGPU", "")>;
|
|
def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
|
|
!if(enableDisasm, "GFX90A", "")>;
|
|
def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
|
|
!if(enableDisasm, "AMDGPU", "")>;
|
|
}
|
|
}
|
|
let VAddrDwords = 2 in {
|
|
if op.HAS_BASE then {
|
|
def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>;
|
|
def _V2_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_64>;
|
|
def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>;
|
|
def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>;
|
|
}
|
|
}
|
|
let VAddrDwords = 3 in {
|
|
if op.HAS_BASE then {
|
|
def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>;
|
|
def _V3_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_96>;
|
|
def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>;
|
|
def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>;
|
|
}
|
|
}
|
|
let VAddrDwords = 4 in {
|
|
if op.HAS_BASE then {
|
|
def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>;
|
|
def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>;
|
|
def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
|
|
def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
|
|
!if(enableDisasm, "AMDGPU", "")>;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Store <mimgopc op, string asm, bit has_d16, bit mip = 0> {
|
|
def "" : MIMGBaseOpcode {
|
|
let Store = 1;
|
|
let LodOrClampOrMip = mip;
|
|
let HasD16 = has_d16;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
|
|
let VDataDwords = 1 in
|
|
defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>;
|
|
let VDataDwords = 3 in
|
|
defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>;
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>;
|
|
let VDataDwords = 5 in
|
|
defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>;
|
|
}
|
|
}
|
|
|
|
class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, string dns="">
|
|
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
|
|
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
|
|
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
|
|
}
|
|
|
|
class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, string dns="">
|
|
: MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata,
|
|
addr_rc:$vaddr, SReg_256:$srsrc,
|
|
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, LWE:$lwe, DA:$da);
|
|
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
|
|
}
|
|
|
|
class MIMG_Atomic_si<mimgopc op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, bit enableDasm = 0>
|
|
: MIMG_Atomic_gfx6789_base<op.SI, asm, data_rc, addr_rc,
|
|
!if(enableDasm, "GFX6GFX7", "")> {
|
|
let AssemblerPredicate = isGFX6GFX7;
|
|
}
|
|
|
|
class MIMG_Atomic_vi<mimgopc op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, bit enableDasm = 0>
|
|
: MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
|
|
let AssemblerPredicate = isGFX8GFX9NotGFX90A;
|
|
let MIMGEncoding = MIMGEncGfx8;
|
|
}
|
|
|
|
class MIMG_Atomic_gfx90a<mimgopc op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, bit enableDasm = 0>
|
|
: MIMG_Atomic_gfx90a_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX90A", "")> {
|
|
let AssemblerPredicate = isGFX90APlus;
|
|
let MIMGEncoding = MIMGEncGfx90a;
|
|
}
|
|
|
|
class MIMG_Atomic_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, RegisterClass AddrRC,
|
|
bit enableDisasm = 0>
|
|
: MIMG_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst),
|
|
!if(enableDisasm, "AMDGPU", "")> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
|
|
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe);
|
|
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
|
|
}
|
|
|
|
class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, int num_addrs,
|
|
bit enableDisasm = 0>
|
|
: MIMG_nsa_gfx10<!cast<int>(op.BASE), (outs DataRC:$vdst), num_addrs,
|
|
!if(enableDisasm, "AMDGPU", "")> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = !con((ins DataRC:$vdata),
|
|
AddrIns,
|
|
(ins SReg_256:$srsrc, DMask:$dmask,
|
|
Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe));
|
|
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
|
|
}
|
|
|
|
multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
|
|
RegisterClass data_rc,
|
|
bit enableDasm = 0,
|
|
bit isFP = 0> {
|
|
let hasSideEffects = 1, // FIXME: remove this
|
|
mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1,
|
|
ssamp = 0, FPAtomic = isFP in {
|
|
let VAddrDwords = 1 in {
|
|
if op.HAS_SI then {
|
|
def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
}
|
|
if op.HAS_VI then {
|
|
def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
def _V1_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
}
|
|
if op.HAS_BASE then {
|
|
def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
}
|
|
}
|
|
let VAddrDwords = 2 in {
|
|
if op.HAS_SI then {
|
|
def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
|
|
}
|
|
if op.HAS_VI then {
|
|
def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
|
|
def _V2_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_64, 0>;
|
|
}
|
|
if op.HAS_BASE then {
|
|
def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>;
|
|
def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>;
|
|
}
|
|
}
|
|
let VAddrDwords = 3 in {
|
|
if op.HAS_SI then {
|
|
def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
|
|
}
|
|
if op.HAS_VI then {
|
|
def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
|
|
def _V3_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_96, 0>;
|
|
}
|
|
if op.HAS_BASE then {
|
|
def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>;
|
|
def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>;
|
|
}
|
|
}
|
|
let VAddrDwords = 4 in {
|
|
if op.HAS_SI then {
|
|
def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
|
|
}
|
|
if op.HAS_VI then {
|
|
def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
|
|
def _V4_gfx90a : MIMG_Atomic_gfx90a <op, asm, data_rc, VReg_128, 0>;
|
|
}
|
|
if op.HAS_BASE then {
|
|
def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>;
|
|
def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics
|
|
let IsAtomicRet = 1 in {
|
|
def "" : MIMGBaseOpcode {
|
|
let Atomic = 1;
|
|
let AtomicX2 = isCmpSwap;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
|
|
// _V* variants have different dst size, but the size is encoded implicitly,
|
|
// using dmask and tfe. Only 32-bit variant is registered with disassembler.
|
|
// Other variants are reconstructed by disassembler using dmask and tfe.
|
|
let VDataDwords = !if(isCmpSwap, 2, 1) in
|
|
defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>;
|
|
let VDataDwords = !if(isCmpSwap, 4, 2) in
|
|
defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>;
|
|
}
|
|
} // End IsAtomicRet = 1
|
|
}
|
|
|
|
class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
|
|
RegisterClass src_rc, string dns="">
|
|
: MIMG_gfx6789 <op.BASE, (outs dst_rc:$vdata), dns> {
|
|
let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
|
|
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$tfe$lwe$da"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc,
|
|
RegisterClass src_rc, string dns="">
|
|
: MIMG_gfx90a<op.BASE, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
|
|
let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
|
|
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, LWE:$lwe, DA:$da),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$cpol$r128$lwe$da"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Sampler_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, RegisterClass AddrRC,
|
|
string dns="">
|
|
: MIMG_gfx10<op.BASE, (outs DataRC:$vdata), dns> {
|
|
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp,
|
|
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
|
|
#"$cpol$r128$a16$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode,
|
|
RegisterClass DataRC, int num_addrs,
|
|
string dns="">
|
|
: MIMG_nsa_gfx10<op.BASE, (outs DataRC:$vdata), num_addrs, dns> {
|
|
let InOperandList = !con(AddrIns,
|
|
(ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask,
|
|
Dim:$dim, UNorm:$unorm, CPol:$cpol,
|
|
R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm"
|
|
#"$cpol$r128$a16$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMGAddrSize<int dw, bit enable_disasm> {
|
|
int NumWords = dw;
|
|
|
|
RegisterClass RegClass = !if(!le(NumWords, 0), ?,
|
|
!if(!eq(NumWords, 1), VGPR_32,
|
|
!if(!eq(NumWords, 2), VReg_64,
|
|
!if(!eq(NumWords, 3), VReg_96,
|
|
!if(!eq(NumWords, 4), VReg_128,
|
|
!if(!eq(NumWords, 5), VReg_160,
|
|
!if(!eq(NumWords, 6), VReg_192,
|
|
!if(!eq(NumWords, 7), VReg_224,
|
|
!if(!le(NumWords, 8), VReg_256,
|
|
!if(!le(NumWords, 16), VReg_512, ?))))))))));
|
|
|
|
// Whether the instruction variant with this vaddr size should be enabled for
|
|
// the auto-generated disassembler.
|
|
bit Disassemble = enable_disasm;
|
|
}
|
|
|
|
// Return whether x is in lst.
|
|
class isIntInList<int x, list<int> lst> {
|
|
bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y)));
|
|
}
|
|
|
|
// Return whether a value inside the range [min, max] (endpoints inclusive)
|
|
// is in the given list.
|
|
class isRangeInList<int min, int max, list<int> lst> {
|
|
bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max))));
|
|
}
|
|
|
|
class MIMGAddrSizes_dw_range<list<int> range> {
|
|
int Min = !head(range);
|
|
int Max = !if(!empty(!tail(range)), Min, !head(!tail(range)));
|
|
}
|
|
|
|
class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
|
|
// List of all possible numbers of address words, taking all combinations of
|
|
// A16 and image dimension into account (note: no MSAA, since this is for
|
|
// sample/gather ops).
|
|
list<int> AllNumAddrWords =
|
|
!foreach(dw, !if(sample.Gradients,
|
|
!if(!eq(sample.LodOrClamp, ""),
|
|
[2, 3, 4, 5, 6, 7, 8, 9],
|
|
[2, 3, 4, 5, 6, 7, 8, 9, 10]),
|
|
!if(!eq(sample.LodOrClamp, ""),
|
|
[1, 2, 3],
|
|
[1, 2, 3, 4])),
|
|
!add(dw, !size(sample.ExtraAddrArgs)));
|
|
|
|
// Generate machine instructions based on possible register classes for the
|
|
// required numbers of address words. The disassembler defaults to the
|
|
// smallest register class.
|
|
list<MIMGAddrSize> MachineInstrs =
|
|
!foldl([]<MIMGAddrSize>,
|
|
!foreach(range,
|
|
// V4 is generated for V3 and V4
|
|
// V8 is generated for V5 through V8
|
|
// V16 is generated for V9 through V16
|
|
[[1],[2],[3],[3,4],[5],[6],[7],[5,8],[9,16]],
|
|
MIMGAddrSizes_dw_range<range>),
|
|
lhs, dw,
|
|
!if(isRangeInList<dw.Min, dw.Max, AllNumAddrWords>.ret,
|
|
!listconcat(lhs, [MIMGAddrSize<dw.Max, !empty(lhs)>]),
|
|
lhs));
|
|
|
|
// For NSA, generate machine instructions for all possible numbers of words
|
|
// except 1 (which is already covered by the non-NSA case).
|
|
// The disassembler defaults to the largest number of arguments among the
|
|
// variants with the same number of NSA words, and custom code then derives
|
|
// the exact variant based on the sample variant and the image dimension.
|
|
list<MIMGAddrSize> NSAInstrs =
|
|
!foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group,
|
|
!listconcat(prev,
|
|
!foldl([]<MIMGAddrSize>, nsa_group, lhs, dw,
|
|
!if(isIntInList<dw, AllNumAddrWords>.ret,
|
|
!listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]),
|
|
lhs))));
|
|
}
|
|
|
|
multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
|
|
AMDGPUSampleVariant sample, RegisterClass dst_rc,
|
|
bit enableDisasm = 0,
|
|
bit ExtendedImageInst = 1> {
|
|
foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
|
|
let VAddrDwords = addr.NumWords in {
|
|
if op.HAS_BASE then {
|
|
def _V # addr.NumWords
|
|
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
if !not(ExtendedImageInst) then
|
|
def _V # addr.NumWords # _gfx90a
|
|
: MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,
|
|
!if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>;
|
|
def _V # addr.NumWords # _gfx10
|
|
: MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
}
|
|
}
|
|
}
|
|
|
|
foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
|
|
let VAddrDwords = addr.NumWords in {
|
|
if op.HAS_BASE then {
|
|
def _V # addr.NumWords # _nsa_gfx10
|
|
: MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample>
|
|
: MIMGBaseOpcode {
|
|
let Sampler = 1;
|
|
let NumExtraArgs = !size(sample.ExtraAddrArgs);
|
|
let Gradients = sample.Gradients;
|
|
let LodOrClampOrMip = !ne(sample.LodOrClamp, "");
|
|
}
|
|
|
|
multiclass MIMG_Sampler <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
|
|
bit isG16 = 0, bit isGetLod = 0,
|
|
string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", ""),
|
|
bit ExtendedImageInst = !ne(sample.LowerCaseMod, "")> {
|
|
def "" : MIMG_Sampler_BaseOpcode<sample> {
|
|
let HasD16 = !not(isGetLod);
|
|
let G16 = isG16;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
|
|
mayLoad = !not(isGetLod) in {
|
|
let VDataDwords = 1 in
|
|
defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1, ExtendedImageInst>;
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64, 0, ExtendedImageInst>;
|
|
let VDataDwords = 3 in
|
|
defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96, 0, ExtendedImageInst>;
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 0, ExtendedImageInst>;
|
|
let VDataDwords = 5 in
|
|
defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160, 0, ExtendedImageInst>;
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Sampler_WQM <mimgopc op, AMDGPUSampleVariant sample>
|
|
: MIMG_Sampler<op, sample, 1>;
|
|
|
|
multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
|
|
string asm = "image_gather4"#sample.LowerCaseMod> {
|
|
def "" : MIMG_Sampler_BaseOpcode<sample> {
|
|
let HasD16 = 1;
|
|
let Gather4 = 1;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
|
|
Gather4 = 1 in {
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>;
|
|
let VDataDwords = 5 in
|
|
defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
|
|
: MIMG_Gather<op, sample, 1>;
|
|
|
|
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC, bit A16>
|
|
: MIMG_gfx10<op.BASE, (outs VReg_128:$vdata), "AMDGPU"> {
|
|
|
|
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc),
|
|
!if(A16, (ins GFX10A16:$a16), (ins)));
|
|
let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", "");
|
|
|
|
let nsa = 0;
|
|
}
|
|
|
|
class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs, bit A16>
|
|
: MIMG_nsa_gfx10<op.BASE, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> {
|
|
let InOperandList = !con(nsah.AddrIns,
|
|
(ins SReg_128:$srsrc),
|
|
!if(A16, (ins GFX10A16:$a16), (ins)));
|
|
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", "");
|
|
}
|
|
|
|
multiclass MIMG_IntersectRay<mimgopc op, string opcode, int num_addrs, bit A16> {
|
|
def "" : MIMGBaseOpcode;
|
|
let SubtargetPredicate = HasGFX10_AEncoding,
|
|
AssemblerPredicate = HasGFX10_AEncoding,
|
|
AsmMatchConverter = !if(A16, "cvtIntersectRay", ""),
|
|
dmask = 0xf,
|
|
unorm = 1,
|
|
d16 = 0,
|
|
cpol = 0,
|
|
tfe = 0,
|
|
lwe = 0,
|
|
r128 = 1,
|
|
ssamp = 0,
|
|
dim = {0, 0, 0},
|
|
a16 = A16,
|
|
d16 = 0,
|
|
BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
|
|
VDataDwords = 4 in {
|
|
// TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple,
|
|
// when we only need 9, 11 or 12 depending on A16 field and ptr size.
|
|
def "_sa" : MIMG_IntersectRay_gfx10<op, opcode, MIMGAddrSize<num_addrs, 0>.RegClass, A16> {
|
|
let VAddrDwords = !srl(MIMGAddrSize<num_addrs, 0>.RegClass.Size, 5);
|
|
}
|
|
def _nsa : MIMG_IntersectRay_nsa_gfx10<op, opcode, num_addrs, A16> {
|
|
let VAddrDwords = num_addrs;
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MIMG Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm IMAGE_LOAD : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>;
|
|
defm IMAGE_LOAD_MIP : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>;
|
|
defm IMAGE_LOAD_PCK : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>;
|
|
defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>;
|
|
defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>;
|
|
defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>;
|
|
defm IMAGE_STORE : MIMG_Store <mimgopc<0x08>, "image_store", 1>;
|
|
defm IMAGE_STORE_MIP : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>;
|
|
defm IMAGE_STORE_PCK : MIMG_Store <mimgopc<0x0a>, "image_store_pck", 0>;
|
|
defm IMAGE_STORE_MIP_PCK : MIMG_Store <mimgopc<0x0b>, "image_store_mip_pck", 0, 1>;
|
|
|
|
defm IMAGE_GET_RESINFO : MIMG_NoSampler <mimgopc<0x0e>, "image_get_resinfo", 0, 1, 1>;
|
|
|
|
defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimgopc<0x0f, 0x10, 0x0f>, "image_atomic_swap">;
|
|
defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimgopc<0x10, 0x11, 0x10>, "image_atomic_cmpswap", 1>;
|
|
defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimgopc<0x11, 0x12, 0x11>, "image_atomic_add">;
|
|
defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimgopc<0x12, 0x13, 0x12>, "image_atomic_sub">;
|
|
defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x13>, "image_atomic_rsub">;
|
|
defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimgopc<0x14>, "image_atomic_smin">;
|
|
defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimgopc<0x15>, "image_atomic_umin">;
|
|
defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimgopc<0x16>, "image_atomic_smax">;
|
|
defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimgopc<0x17>, "image_atomic_umax">;
|
|
defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimgopc<0x18>, "image_atomic_and">;
|
|
defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">;
|
|
defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">;
|
|
defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">;
|
|
defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">;
|
|
defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 0, 1>;
|
|
defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>;
|
|
defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>;
|
|
|
|
defm IMAGE_SAMPLE : MIMG_Sampler_WQM <mimgopc<0x20>, AMDGPUSample>;
|
|
let OtherPredicates = [HasExtendedImageInsts] in {
|
|
defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <mimgopc<0x21>, AMDGPUSample_cl>;
|
|
defm IMAGE_SAMPLE_D : MIMG_Sampler <mimgopc<0x22>, AMDGPUSample_d>;
|
|
defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <mimgopc<0x23>, AMDGPUSample_d_cl>;
|
|
defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <mimgopc<0xa2>, AMDGPUSample_d, 0, 1>;
|
|
defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <mimgopc<0xa3>, AMDGPUSample_d_cl, 0, 1>;
|
|
defm IMAGE_SAMPLE_L : MIMG_Sampler <mimgopc<0x24>, AMDGPUSample_l>;
|
|
defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <mimgopc<0x25>, AMDGPUSample_b>;
|
|
defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <mimgopc<0x26>, AMDGPUSample_b_cl>;
|
|
defm IMAGE_SAMPLE_LZ : MIMG_Sampler <mimgopc<0x27>, AMDGPUSample_lz>;
|
|
defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <mimgopc<0x28>, AMDGPUSample_c>;
|
|
defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <mimgopc<0x29>, AMDGPUSample_c_cl>;
|
|
defm IMAGE_SAMPLE_C_D : MIMG_Sampler <mimgopc<0x2a>, AMDGPUSample_c_d>;
|
|
defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <mimgopc<0x2b>, AMDGPUSample_c_d_cl>;
|
|
defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <mimgopc<0xaa>, AMDGPUSample_c_d, 0, 1>;
|
|
defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <mimgopc<0xab>, AMDGPUSample_c_d_cl, 0, 1>;
|
|
defm IMAGE_SAMPLE_C_L : MIMG_Sampler <mimgopc<0x2c>, AMDGPUSample_c_l>;
|
|
defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <mimgopc<0x2d>, AMDGPUSample_c_b>;
|
|
defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <mimgopc<0x2e>, AMDGPUSample_c_b_cl>;
|
|
defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <mimgopc<0x2f>, AMDGPUSample_c_lz>;
|
|
defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <mimgopc<0x30>, AMDGPUSample_o>;
|
|
defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <mimgopc<0x31>, AMDGPUSample_cl_o>;
|
|
defm IMAGE_SAMPLE_D_O : MIMG_Sampler <mimgopc<0x32>, AMDGPUSample_d_o>;
|
|
defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <mimgopc<0x33>, AMDGPUSample_d_cl_o>;
|
|
defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <mimgopc<0xb2>, AMDGPUSample_d_o, 0, 1>;
|
|
defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xb3>, AMDGPUSample_d_cl_o, 0, 1>;
|
|
defm IMAGE_SAMPLE_L_O : MIMG_Sampler <mimgopc<0x34>, AMDGPUSample_l_o>;
|
|
defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <mimgopc<0x35>, AMDGPUSample_b_o>;
|
|
defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x36>, AMDGPUSample_b_cl_o>;
|
|
defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <mimgopc<0x37>, AMDGPUSample_lz_o>;
|
|
defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <mimgopc<0x38>, AMDGPUSample_c_o>;
|
|
defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <mimgopc<0x39>, AMDGPUSample_c_cl_o>;
|
|
defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <mimgopc<0x3a>, AMDGPUSample_c_d_o>;
|
|
defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <mimgopc<0x3b>, AMDGPUSample_c_d_cl_o>;
|
|
defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <mimgopc<0xba>, AMDGPUSample_c_d_o, 0, 1>;
|
|
defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <mimgopc<0xbb>, AMDGPUSample_c_d_cl_o, 0, 1>;
|
|
defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <mimgopc<0x3c>, AMDGPUSample_c_l_o>;
|
|
defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <mimgopc<0x3e>, AMDGPUSample_c_b_cl_o>;
|
|
defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <mimgopc<0x3d>, AMDGPUSample_c_b_o>;
|
|
defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <mimgopc<0x3f>, AMDGPUSample_c_lz_o>;
|
|
defm IMAGE_GATHER4 : MIMG_Gather_WQM <mimgopc<0x40>, AMDGPUSample>;
|
|
defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <mimgopc<0x41>, AMDGPUSample_cl>;
|
|
defm IMAGE_GATHER4_L : MIMG_Gather <mimgopc<0x44>, AMDGPUSample_l>;
|
|
defm IMAGE_GATHER4_B : MIMG_Gather_WQM <mimgopc<0x45>, AMDGPUSample_b>;
|
|
defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <mimgopc<0x46>, AMDGPUSample_b_cl>;
|
|
defm IMAGE_GATHER4_LZ : MIMG_Gather <mimgopc<0x47>, AMDGPUSample_lz>;
|
|
defm IMAGE_GATHER4_C : MIMG_Gather_WQM <mimgopc<0x48>, AMDGPUSample_c>;
|
|
defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <mimgopc<0x49>, AMDGPUSample_c_cl>;
|
|
defm IMAGE_GATHER4_C_L : MIMG_Gather <mimgopc<0x4c>, AMDGPUSample_c_l>;
|
|
defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <mimgopc<0x4d>, AMDGPUSample_c_b>;
|
|
defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <mimgopc<0x4e>, AMDGPUSample_c_b_cl>;
|
|
defm IMAGE_GATHER4_C_LZ : MIMG_Gather <mimgopc<0x4f>, AMDGPUSample_c_lz>;
|
|
defm IMAGE_GATHER4_O : MIMG_Gather_WQM <mimgopc<0x50>, AMDGPUSample_o>;
|
|
defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <mimgopc<0x51>, AMDGPUSample_cl_o>;
|
|
defm IMAGE_GATHER4_L_O : MIMG_Gather <mimgopc<0x54>, AMDGPUSample_l_o>;
|
|
defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <mimgopc<0x55>, AMDGPUSample_b_o>;
|
|
defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <mimgopc<0x56>, AMDGPUSample_b_cl_o>;
|
|
defm IMAGE_GATHER4_LZ_O : MIMG_Gather <mimgopc<0x57>, AMDGPUSample_lz_o>;
|
|
defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <mimgopc<0x58>, AMDGPUSample_c_o>;
|
|
defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <mimgopc<0x59>, AMDGPUSample_c_cl_o>;
|
|
defm IMAGE_GATHER4_C_L_O : MIMG_Gather <mimgopc<0x5c>, AMDGPUSample_c_l_o>;
|
|
defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <mimgopc<0x5d>, AMDGPUSample_c_b_o>;
|
|
defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <mimgopc<0x5e>, AMDGPUSample_c_b_cl_o>;
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defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <mimgopc<0x5f>, AMDGPUSample_c_lz_o>;
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//defm IMAGE_GATHER4H : MIMG_Gather_WQM <mimgopc<0x61>, ?>;
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defm IMAGE_GET_LOD : MIMG_Sampler <mimgopc<0x60>, AMDGPUSample, 1, 0, 1, "image_get_lod">;
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defm IMAGE_SAMPLE_CD : MIMG_Sampler <mimgopc<0x68>, AMDGPUSample_cd>;
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defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <mimgopc<0x69>, AMDGPUSample_cd_cl>;
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defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <mimgopc<0x6a>, AMDGPUSample_c_cd>;
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defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <mimgopc<0x6b>, AMDGPUSample_c_cd_cl>;
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defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <mimgopc<0x6c>, AMDGPUSample_cd_o>;
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defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <mimgopc<0x6d>, AMDGPUSample_cd_cl_o>;
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defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <mimgopc<0x6e>, AMDGPUSample_c_cd_o>;
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defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <mimgopc<0x6f>, AMDGPUSample_c_cd_cl_o>;
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defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <mimgopc<0xe8>, AMDGPUSample_cd, 0, 1>;
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defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <mimgopc<0xe9>, AMDGPUSample_cd_cl, 0, 1>;
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defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <mimgopc<0xea>, AMDGPUSample_c_cd, 0, 1>;
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defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <mimgopc<0xeb>, AMDGPUSample_c_cd_cl, 0, 1>;
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defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <mimgopc<0xec>, AMDGPUSample_cd_o, 0, 1>;
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defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xed>, AMDGPUSample_cd_cl_o, 0, 1>;
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defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <mimgopc<0xee>, AMDGPUSample_c_cd_o, 0, 1>;
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defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <mimgopc<0xef>, AMDGPUSample_c_cd_cl_o, 0, 1>;
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} // End OtherPredicates = [HasExtendedImageInsts]
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//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
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//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
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let SubtargetPredicate = HasGFX10_AEncoding in
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defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>;
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defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 11, 0>;
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defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 8, 1>;
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defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 12, 0>;
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defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 9, 1>;
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/********** ========================================= **********/
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/********** Table of dimension-aware image intrinsics **********/
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/********** ========================================= **********/
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class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> {
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Intrinsic Intr = I;
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MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod));
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AMDGPUDimProps Dim = I.P.Dim;
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AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>;
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bits<8> NumGradients = DimEval.NumGradientArgs;
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bits<8> NumDmask = DimEval.NumDmaskArgs;
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bits<8> NumData = DimEval.NumDataArgs;
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bits<8> NumVAddrs = DimEval.NumVAddrArgs;
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bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1);
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bits<8> DMaskIndex = DimEval.DmaskArgIndex;
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bits<8> VAddrStart = DimEval.VAddrArgIndex;
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bits<8> GradientStart = DimEval.GradientArgIndex;
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bits<8> CoordStart = DimEval.CoordArgIndex;
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bits<8> LodIndex = DimEval.LodArgIndex;
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bits<8> MipIndex = DimEval.MipArgIndex;
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bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs);
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bits<8> RsrcIndex = DimEval.RsrcArgIndex;
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bits<8> SampIndex = DimEval.SampArgIndex;
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bits<8> UnormIndex = DimEval.UnormArgIndex;
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bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex;
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bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex;
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bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes,
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!foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny)));
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bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0));
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}
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def ImageDimIntrinsicTable : GenericTable {
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let FilterClass = "ImageDimIntrinsicInfo";
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let Fields = ["Intr", "BaseOpcode", "Dim", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs",
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"DMaskIndex", "VAddrStart", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd",
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"RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
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"GradientTyArg", "CoordTyArg"];
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string TypeOf_BaseOpcode = "MIMGBaseOpcode";
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string TypeOf_Dim = "MIMGDim";
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let PrimaryKey = ["Intr"];
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let PrimaryKeyName = "getImageDimIntrinsicInfo";
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let PrimaryKeyEarlyOut = 1;
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}
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def getImageDimInstrinsicByBaseOpcode : SearchIndex {
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let Table = ImageDimIntrinsicTable;
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let Key = ["BaseOpcode", "Dim"];
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}
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foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
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AMDGPUImageDimAtomicIntrinsics) in {
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def : ImageDimIntrinsicInfo<intr>;
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}
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// L to LZ Optimization Mapping
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def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>;
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def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>;
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def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>;
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def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>;
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def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>;
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def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>;
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def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>;
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def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>;
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// MIP to NONMIP Optimization Mapping
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def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>;
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def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>;
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// G to G16 Optimization Mapping
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def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>;
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def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>;
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