Hrvoje Varga 6bf6a83a4c [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions ... Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719		2016-08-04 11:22:52 +00:00
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AArch64	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AMDGPU	[AMDGPU] refactor DS instruction definitions. NFC.	2016-08-01 14:21:30 +00:00
ARM	[ARM] Saturation instructions are DSP-only	2016-07-25 22:25:25 +00:00
Hexagon	[Hexagon] Treat all conditional branches as predicted (not-taken by default)	2016-05-09 18:22:07 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions	2016-08-04 11:22:52 +00:00
PowerPC	This reverts commit r265505.	2016-04-28 20:00:42 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities	2016-07-11 18:45:03 +00:00
X86	Add new flag and intrinsic support for MWAITX and MONITORX instructions	2016-05-18 11:59:12 +00:00
XCore