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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
89 lines
3.0 KiB
C++
89 lines
3.0 KiB
C++
//===-- PatchableFunction.cpp - Patchable prologues for LLVM -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements edits function bodies in place to support the
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// "patchable-function" attribute.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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struct PatchableFunction : public MachineFunctionPass {
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static char ID; // Pass identification, replacement for typeid
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PatchableFunction() : MachineFunctionPass(ID) {
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initializePatchableFunctionPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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}
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/// Returns true if instruction \p MI will not result in actual machine code
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/// instructions.
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static bool doesNotGeneratecode(const MachineInstr &MI) {
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// TODO: Introduce an MCInstrDesc flag for this
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switch (MI.getOpcode()) {
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default: return false;
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case TargetOpcode::CFI_INSTRUCTION:
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case TargetOpcode::EH_LABEL:
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case TargetOpcode::GC_LABEL:
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case TargetOpcode::DBG_VALUE:
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case TargetOpcode::DBG_LABEL:
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return true;
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}
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}
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bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
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if (!MF.getFunction().hasFnAttribute("patchable-function"))
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return false;
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#ifndef NDEBUG
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Attribute PatchAttr = MF.getFunction().getFnAttribute("patchable-function");
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StringRef PatchType = PatchAttr.getValueAsString();
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assert(PatchType == "prologue-short-redirect" && "Only possibility today!");
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#endif
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auto &FirstMBB = *MF.begin();
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MachineBasicBlock::iterator FirstActualI = FirstMBB.begin();
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for (; doesNotGeneratecode(*FirstActualI); ++FirstActualI)
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assert(FirstActualI != FirstMBB.end());
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auto *TII = MF.getSubtarget().getInstrInfo();
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auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
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TII->get(TargetOpcode::PATCHABLE_OP))
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.addImm(2)
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.addImm(FirstActualI->getOpcode());
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for (auto &MO : FirstActualI->operands())
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MIB.add(MO);
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FirstActualI->eraseFromParent();
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MF.ensureAlignment(4);
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return true;
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}
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char PatchableFunction::ID = 0;
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char &llvm::PatchableFunctionID = PatchableFunction::ID;
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INITIALIZE_PASS(PatchableFunction, "patchable-function",
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"Implement the 'patchable-function' attribute", false, false)
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