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335 lines
21 KiB
TableGen
335 lines
21 KiB
TableGen
//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Freescale e500mc 32-bit
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// Power processor.
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//
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// All information is derived from the "e500mc Core Reference Manual",
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// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
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//
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//===----------------------------------------------------------------------===//
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// Relevant functional units in the Freescale e500mc core:
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//
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// * Decode & Dispatch
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// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
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def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 1
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def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 2
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// * Execute
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// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
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// Some instructions can only execute in SFX0 but not SFX1.
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// The CFX has a bypass path, allowing non-divide instructions to execute
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// while a divide instruction is executed.
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def E500mc_SFX0 : FuncUnit; // Simple unit 0
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def E500mc_SFX1 : FuncUnit; // Simple unit 1
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def E500mc_BU : FuncUnit; // Branch unit
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def E500mc_CFX_DivBypass
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: FuncUnit; // CFX divide bypass path
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def E500mc_CFX_0 : FuncUnit; // CFX pipeline
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def E500mc_LSU_0 : FuncUnit; // LSU pipeline
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def E500mc_FPU_0 : FuncUnit; // FPU pipeline
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def E500mc_GPR_Bypass : Bypass;
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def E500mc_FPR_Bypass : Bypass;
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def E500mc_CR_Bypass : Bypass;
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def PPCE500mcItineraries : ProcessorItineraries<
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[E500mc_DIS0, E500mc_DIS1, E500mc_SFX0, E500mc_SFX1, E500mc_BU, E500mc_CFX_DivBypass,
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E500mc_CFX_0, E500mc_LSU_0, E500mc_FPU_0],
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[E500mc_CR_Bypass, E500mc_GPR_Bypass, E500mc_FPR_Bypass], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1], // Latency = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1], // Latency = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1, 1], // Latency = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass,
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E500mc_CR_Bypass]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[5, 1, 1], // Latency = 1 or 2
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[E500mc_CR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_CFX_0], 0>,
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InstrStage<14, [E500mc_CFX_DivBypass]>],
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[17, 1, 1], // Latency=4..35, Repeat= 4..35
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<8, [E500mc_FPU_0]>],
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[11], // Latency = 8
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[E500mc_FPR_Bypass]>,
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InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<8, [E500mc_FPU_0]>],
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[11, 1, 1], // Latency = 8
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[NoBypass, NoBypass, NoBypass]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_CFX_0]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1], // Latency = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1], // Latency = 1
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<2, [E500mc_SFX0]>],
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[5, 1], // Latency = 2, Repeat rate = 2
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_BU]>],
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[4, 1], // Latency = 1
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_BU]>],
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[4, 1, 1], // Latency = 1
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[E500mc_CR_Bypass,
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E500mc_CR_Bypass, E500mc_CR_Bypass]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_BU]>],
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[4, 1], // Latency = 1
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[E500mc_CR_Bypass, E500mc_CR_Bypass]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1, 1], // Latency = 1
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[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3, Repeat rate = 1
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1, 1], // Latency = 3
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1, 1], // Latency = 3
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[7, 1, 1], // Latency = 4
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[E500mc_FPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[7, 1, 1], // Latency = 4
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[E500mc_FPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[7, 1, 1], // Latency = 4
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[E500mc_FPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[7, 1], // Latency = r+3
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<3, [E500mc_LSU_0]>],
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[6, 1, 1], // Latency = 3, Repeat rate = 3
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[E500mc_GPR_Bypass,
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E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0]>]>,
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InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<4, [E500mc_SFX0]>],
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[7, 1],
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<2, [E500mc_SFX0, E500mc_SFX1]>],
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[5, 1], // Latency = 2, Repeat rate = 4
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0]>],
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[5, 1],
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_LSU_0], 0>]>,
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InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<5, [E500mc_SFX0]>],
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[8, 1],
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[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
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InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<5, [E500mc_SFX0]>],
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[8, 1],
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[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
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InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<4, [E500mc_SFX0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<4, [E500mc_SFX0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
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InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<4, [E500mc_SFX0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<1, [E500mc_SFX0]>],
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[4, 1],
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[NoBypass, E500mc_GPR_Bypass]>,
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InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<2, [E500mc_FPU_0]>],
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[11, 1, 1], // Latency = 8, Repeat rate = 2
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[E500mc_FPR_Bypass,
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E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
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InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<4, [E500mc_FPU_0]>],
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[13, 1, 1], // Latency = 10, Repeat rate = 4
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|
[E500mc_FPR_Bypass,
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|
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
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InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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InstrStage<2, [E500mc_FPU_0]>],
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|
[11, 1, 1], // Latency = 8, Repeat rate = 2
|
|
[E500mc_CR_Bypass,
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|
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
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|
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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|
InstrStage<68, [E500mc_FPU_0]>],
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|
[71, 1, 1], // Latency = 68, Repeat rate = 68
|
|
[E500mc_FPR_Bypass,
|
|
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
|
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
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|
InstrStage<38, [E500mc_FPU_0]>],
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|
[41, 1, 1], // Latency = 38, Repeat rate = 38
|
|
[E500mc_FPR_Bypass,
|
|
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
|
InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
|
InstrStage<4, [E500mc_FPU_0]>],
|
|
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4
|
|
[E500mc_FPR_Bypass,
|
|
E500mc_FPR_Bypass, E500mc_FPR_Bypass,
|
|
E500mc_FPR_Bypass]>,
|
|
InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
|
InstrStage<38, [E500mc_FPU_0]>],
|
|
[41, 1], // Latency = 38, Repeat rate = 38
|
|
[E500mc_FPR_Bypass, E500mc_FPR_Bypass]>
|
|
]>;
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|
|
|
// ===---------------------------------------------------------------------===//
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|
// e500mc machine model for scheduling and other instruction cost heuristics.
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|
|
|
def PPCE500mcModel : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let LoadLatency = 5; // Optimistic load latency assuming bypass.
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|
// This is overriden by OperandCycles if the
|
|
// Itineraries are queried instead.
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|
|
|
let CompleteModel = 0;
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|
|
|
let Itineraries = PPCE500mcItineraries;
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|
}
|