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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
88 lines
3.5 KiB
TableGen
88 lines
3.5 KiB
TableGen
//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel VMX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VMX instructions
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let SchedRW = [WriteSystem] in {
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// 66 0F 38 80
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def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
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"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[Not64BitMode]>;
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def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
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"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[In64BitMode]>;
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// 66 0F 38 81
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def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
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"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[Not64BitMode]>;
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def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
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"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
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Requires<[In64BitMode]>;
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// 0F 01 C1
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def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
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def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
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"vmclear\t$vmcs", []>, PD;
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// OF 01 D4
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def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
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// 0F 01 C2
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def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
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// 0F 01 C3
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def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
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def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
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"vmptrld\t$vmcs", []>, PS;
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def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs),
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"vmptrst\t$vmcs", []>, PS;
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def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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let mayStore = 1 in {
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def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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} // mayStore
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def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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let mayLoad = 1 in {
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def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
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NotMemoryFoldable;
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def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
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NotMemoryFoldable;
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} // mayLoad
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// 0F 01 C4
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def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
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def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
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"vmxon\t$vmxon", []>, XS;
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} // SchedRW
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