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aeed624501
Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
701 lines
36 KiB
TableGen
701 lines
36 KiB
TableGen
//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// InstrSchedModel annotations for out-of-order CPUs.
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// Instructions with folded loads need to read the memory operand immediately,
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// but other register operands don't have to be read until the load is ready.
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// These operands are marked with ReadAfterLd.
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def ReadAfterLd : SchedRead;
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def ReadAfterVecLd : SchedRead;
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def ReadAfterVecXLd : SchedRead;
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def ReadAfterVecYLd : SchedRead;
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// Instructions that move data between general purpose registers and vector
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// registers may be subject to extra latency due to data bypass delays.
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// This SchedRead describes a bypass delay caused by data being moved from the
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// integer unit to the floating point unit.
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def ReadInt2Fpu : SchedRead;
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// Instructions with both a load and a store folded are modeled as a folded
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// load + WriteRMW.
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def WriteRMW : SchedWrite;
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// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
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multiclass X86WriteRes<SchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res, int UOps> {
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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}
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// Most instructions can fold loads, so almost every SchedWrite comes in two
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// variants: With and without a folded load.
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// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
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// with a folded load.
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class X86FoldableSchedWrite : SchedWrite {
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// The SchedWrite to use when a load is folded into the instruction.
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SchedWrite Folded;
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// The SchedRead to tag register operands than don't need to be ready
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// until the folded load has completed.
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SchedRead ReadAfterFold;
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}
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// Multiclass that produces a linked pair of SchedWrites.
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multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
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// Register-Memory operation.
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def Ld : SchedWrite;
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// Register-Register operation.
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def NAME : X86FoldableSchedWrite {
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let Folded = !cast<SchedWrite>(NAME#"Ld");
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let ReadAfterFold = ReadAfter;
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}
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}
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// Helpers to mark SchedWrites as unsupported.
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multiclass X86WriteResUnsupported<SchedWrite SchedRW> {
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let Unsupported = 1 in {
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def : WriteRes<SchedRW, []>;
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}
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}
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multiclass X86WriteResPairUnsupported<X86FoldableSchedWrite SchedRW> {
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let Unsupported = 1 in {
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def : WriteRes<SchedRW, []>;
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def : WriteRes<SchedRW.Folded, []>;
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}
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}
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// Multiclass that wraps X86FoldableSchedWrite for each vector width.
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class X86SchedWriteWidths<X86FoldableSchedWrite sScl,
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X86FoldableSchedWrite s128,
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X86FoldableSchedWrite s256,
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X86FoldableSchedWrite s512> {
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X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.
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X86FoldableSchedWrite MMX = sScl; // MMX operations.
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X86FoldableSchedWrite XMM = s128; // XMM operations.
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X86FoldableSchedWrite YMM = s256; // YMM operations.
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X86FoldableSchedWrite ZMM = s512; // ZMM operations.
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}
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// Multiclass that wraps X86SchedWriteWidths for each fp vector type.
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class X86SchedWriteSizes<X86SchedWriteWidths sPS,
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X86SchedWriteWidths sPD> {
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X86SchedWriteWidths PS = sPS;
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X86SchedWriteWidths PD = sPD;
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}
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// Multiclass that wraps move/load/store triple for a vector width.
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class X86SchedWriteMoveLS<SchedWrite MoveRR,
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SchedWrite LoadRM,
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SchedWrite StoreMR> {
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SchedWrite RR = MoveRR;
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SchedWrite RM = LoadRM;
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SchedWrite MR = StoreMR;
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}
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// Multiclass that wraps X86SchedWriteMoveLS for each vector width.
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class X86SchedWriteMoveLSWidths<X86SchedWriteMoveLS sScl,
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X86SchedWriteMoveLS s128,
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X86SchedWriteMoveLS s256,
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X86SchedWriteMoveLS s512> {
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X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.
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X86SchedWriteMoveLS MMX = sScl; // MMX operations.
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X86SchedWriteMoveLS XMM = s128; // XMM operations.
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X86SchedWriteMoveLS YMM = s256; // YMM operations.
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X86SchedWriteMoveLS ZMM = s512; // ZMM operations.
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}
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// Loads, stores, and moves, not folded with other operations.
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def WriteLoad : SchedWrite;
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def WriteStore : SchedWrite;
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def WriteStoreNT : SchedWrite;
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def WriteMove : SchedWrite;
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def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
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// Arithmetic.
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defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
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defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.
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def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
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def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>;
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def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
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// Integer multiplication
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defm WriteIMul8 : X86SchedWritePair; // Integer 8-bit multiplication.
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defm WriteIMul16 : X86SchedWritePair; // Integer 16-bit multiplication.
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defm WriteIMul16Imm : X86SchedWritePair; // Integer 16-bit multiplication by immediate.
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defm WriteIMul16Reg : X86SchedWritePair; // Integer 16-bit multiplication by register.
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defm WriteIMul32 : X86SchedWritePair; // Integer 32-bit multiplication.
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defm WriteIMul32Imm : X86SchedWritePair; // Integer 32-bit multiplication by immediate.
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defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by register.
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defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.
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defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.
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defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.
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def WriteIMulH : SchedWrite; // Integer multiplication, high part.
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def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
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def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
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defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.
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def WriteCMPXCHGRMW : SchedWrite; // Compare and set, compare and swap.
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def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
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// Integer division.
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defm WriteDiv8 : X86SchedWritePair;
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defm WriteDiv16 : X86SchedWritePair;
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defm WriteDiv32 : X86SchedWritePair;
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defm WriteDiv64 : X86SchedWritePair;
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defm WriteIDiv8 : X86SchedWritePair;
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defm WriteIDiv16 : X86SchedWritePair;
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defm WriteIDiv32 : X86SchedWritePair;
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defm WriteIDiv64 : X86SchedWritePair;
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defm WriteBSF : X86SchedWritePair; // Bit scan forward.
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defm WriteBSR : X86SchedWritePair; // Bit scan reverse.
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defm WritePOPCNT : X86SchedWritePair; // Bit population count.
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defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
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defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
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defm WriteCMOV : X86SchedWritePair; // Conditional move.
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def WriteFCMOV : SchedWrite; // X87 conditional move.
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def WriteSETCC : SchedWrite; // Set register based on condition code.
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def WriteSETCCStore : SchedWrite;
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def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.
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def WriteBitTest : SchedWrite; // Bit Test
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def WriteBitTestImmLd : SchedWrite;
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def WriteBitTestRegLd : SchedWrite;
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def WriteBitTestSet : SchedWrite; // Bit Test + Set
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def WriteBitTestSetImmLd : SchedWrite;
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def WriteBitTestSetRegLd : SchedWrite;
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def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;
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def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;
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// Integer shifts and rotates.
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defm WriteShift : X86SchedWritePair;
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defm WriteShiftCL : X86SchedWritePair;
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defm WriteRotate : X86SchedWritePair;
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defm WriteRotateCL : X86SchedWritePair;
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// Double shift instructions.
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def WriteSHDrri : SchedWrite;
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def WriteSHDrrcl : SchedWrite;
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def WriteSHDmri : SchedWrite;
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def WriteSHDmrcl : SchedWrite;
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// BMI1 BEXTR/BLS, BMI2 BZHI
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defm WriteBEXTR : X86SchedWritePair;
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defm WriteBLS : X86SchedWritePair;
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defm WriteBZHI : X86SchedWritePair;
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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def WriteZero : SchedWrite;
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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defm WriteJump : X86SchedWritePair;
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// Floating point. This covers both scalar and vector operations.
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def WriteFLD0 : SchedWrite;
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def WriteFLD1 : SchedWrite;
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def WriteFLDC : SchedWrite;
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def WriteFLoad : SchedWrite;
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def WriteFLoadX : SchedWrite;
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def WriteFLoadY : SchedWrite;
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def WriteFMaskedLoad : SchedWrite;
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def WriteFMaskedLoadY : SchedWrite;
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def WriteFStore : SchedWrite;
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def WriteFStoreX : SchedWrite;
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def WriteFStoreY : SchedWrite;
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def WriteFStoreNT : SchedWrite;
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def WriteFStoreNTX : SchedWrite;
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def WriteFStoreNTY : SchedWrite;
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def WriteFMaskedStore : SchedWrite;
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def WriteFMaskedStoreY : SchedWrite;
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def WriteFMove : SchedWrite;
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def WriteFMoveX : SchedWrite;
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def WriteFMoveY : SchedWrite;
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defm WriteFAdd : X86SchedWritePair<ReadAfterVecLd>; // Floating point add/sub.
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defm WriteFAddX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point add/sub (XMM).
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defm WriteFAddY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (YMM).
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defm WriteFAddZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point add/sub (ZMM).
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defm WriteFAdd64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double add/sub.
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defm WriteFAdd64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double add/sub (XMM).
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defm WriteFAdd64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (YMM).
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defm WriteFAdd64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double add/sub (ZMM).
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defm WriteFCmp : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare.
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defm WriteFCmpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point compare (XMM).
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defm WriteFCmpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (YMM).
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defm WriteFCmpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point compare (ZMM).
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defm WriteFCmp64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double compare.
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defm WriteFCmp64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double compare (XMM).
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defm WriteFCmp64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (YMM).
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defm WriteFCmp64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double compare (ZMM).
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defm WriteFCom : X86SchedWritePair<ReadAfterVecLd>; // Floating point compare to flags.
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defm WriteFMul : X86SchedWritePair<ReadAfterVecLd>; // Floating point multiplication.
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defm WriteFMulX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point multiplication (XMM).
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defm WriteFMulY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
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defm WriteFMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point multiplication (YMM).
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defm WriteFMul64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double multiplication.
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defm WriteFMul64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double multiplication (XMM).
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defm WriteFMul64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (YMM).
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defm WriteFMul64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double multiplication (ZMM).
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defm WriteFDiv : X86SchedWritePair<ReadAfterVecLd>; // Floating point division.
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defm WriteFDivX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point division (XMM).
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defm WriteFDivY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (YMM).
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defm WriteFDivZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point division (ZMM).
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defm WriteFDiv64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double division.
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defm WriteFDiv64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double division (XMM).
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defm WriteFDiv64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (YMM).
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defm WriteFDiv64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double division (ZMM).
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defm WriteFSqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point square root.
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defm WriteFSqrtX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point square root (XMM).
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defm WriteFSqrtY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (YMM).
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defm WriteFSqrtZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point square root (ZMM).
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defm WriteFSqrt64 : X86SchedWritePair<ReadAfterVecLd>; // Floating point double square root.
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defm WriteFSqrt64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double square root (XMM).
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defm WriteFSqrt64Y : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (YMM).
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defm WriteFSqrt64Z : X86SchedWritePair<ReadAfterVecYLd>; // Floating point double square root (ZMM).
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defm WriteFSqrt80 : X86SchedWritePair<ReadAfterVecLd>; // Floating point long double square root.
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defm WriteFRcp : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal estimate.
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defm WriteFRcpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal estimate (XMM).
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defm WriteFRcpY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (YMM).
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defm WriteFRcpZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal estimate (ZMM).
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defm WriteFRsqrt : X86SchedWritePair<ReadAfterVecLd>; // Floating point reciprocal square root estimate.
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defm WriteFRsqrtX: X86SchedWritePair<ReadAfterVecXLd>; // Floating point reciprocal square root estimate (XMM).
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defm WriteFRsqrtY: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (YMM).
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defm WriteFRsqrtZ: X86SchedWritePair<ReadAfterVecYLd>; // Floating point reciprocal square root estimate (ZMM).
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defm WriteFMA : X86SchedWritePair<ReadAfterVecLd>; // Fused Multiply Add.
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defm WriteFMAX : X86SchedWritePair<ReadAfterVecXLd>; // Fused Multiply Add (XMM).
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defm WriteFMAY : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (YMM).
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defm WriteFMAZ : X86SchedWritePair<ReadAfterVecYLd>; // Fused Multiply Add (ZMM).
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defm WriteDPPD : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double dot product.
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defm WriteDPPS : X86SchedWritePair<ReadAfterVecXLd>; // Floating point single dot product.
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defm WriteDPPSY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point single dot product (YMM).
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defm WriteDPPSZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point single dot product (ZMM).
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defm WriteFSign : X86SchedWritePair<ReadAfterVecLd>; // Floating point fabs/fchs.
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defm WriteFRnd : X86SchedWritePair<ReadAfterVecXLd>; // Floating point rounding.
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defm WriteFRndY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (YMM).
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defm WriteFRndZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point rounding (ZMM).
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defm WriteFLogic : X86SchedWritePair<ReadAfterVecXLd>; // Floating point and/or/xor logicals.
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defm WriteFLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (YMM).
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defm WriteFLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point and/or/xor logicals (ZMM).
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defm WriteFTest : X86SchedWritePair<ReadAfterVecXLd>; // Floating point TEST instructions.
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defm WriteFTestY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (YMM).
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defm WriteFTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point TEST instructions (ZMM).
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defm WriteFShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector shuffles.
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defm WriteFShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (YMM).
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defm WriteFShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector shuffles (ZMM).
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defm WriteFVarShuffle : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector variable shuffles.
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defm WriteFVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (YMM).
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defm WriteFVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector variable shuffles (ZMM).
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defm WriteFBlend : X86SchedWritePair<ReadAfterVecXLd>; // Floating point vector blends.
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defm WriteFBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (YMM).
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defm WriteFBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Floating point vector blends (ZMM).
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defm WriteFVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Fp vector variable blends.
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defm WriteFVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMM).
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defm WriteFVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Fp vector variable blends (YMZMM).
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// FMA Scheduling helper class.
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class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
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// Horizontal Add/Sub (float and integer)
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defm WriteFHAdd : X86SchedWritePair<ReadAfterVecXLd>;
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defm WriteFHAddY : X86SchedWritePair<ReadAfterVecYLd>;
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defm WriteFHAddZ : X86SchedWritePair<ReadAfterVecYLd>;
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defm WritePHAdd : X86SchedWritePair<ReadAfterVecLd>;
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defm WritePHAddX : X86SchedWritePair<ReadAfterVecXLd>;
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defm WritePHAddY : X86SchedWritePair<ReadAfterVecYLd>;
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defm WritePHAddZ : X86SchedWritePair<ReadAfterVecYLd>;
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// Vector integer operations.
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def WriteVecLoad : SchedWrite;
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def WriteVecLoadX : SchedWrite;
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def WriteVecLoadY : SchedWrite;
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def WriteVecLoadNT : SchedWrite;
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def WriteVecLoadNTY : SchedWrite;
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def WriteVecMaskedLoad : SchedWrite;
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def WriteVecMaskedLoadY : SchedWrite;
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def WriteVecStore : SchedWrite;
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def WriteVecStoreX : SchedWrite;
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def WriteVecStoreY : SchedWrite;
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def WriteVecStoreNT : SchedWrite;
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def WriteVecStoreNTY : SchedWrite;
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def WriteVecMaskedStore : SchedWrite;
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def WriteVecMaskedStoreY : SchedWrite;
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def WriteVecMove : SchedWrite;
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def WriteVecMoveX : SchedWrite;
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def WriteVecMoveY : SchedWrite;
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def WriteVecMoveToGpr : SchedWrite;
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def WriteVecMoveFromGpr : SchedWrite;
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defm WriteVecALU : X86SchedWritePair<ReadAfterVecLd>; // Vector integer ALU op, no logicals.
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defm WriteVecALUX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer ALU op, no logicals (XMM).
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defm WriteVecALUY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (YMM).
|
|
defm WriteVecALUZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (ZMM).
|
|
defm WriteVecLogic : X86SchedWritePair<ReadAfterVecLd>; // Vector integer and/or/xor logicals.
|
|
defm WriteVecLogicX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer and/or/xor logicals (XMM).
|
|
defm WriteVecLogicY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (YMM).
|
|
defm WriteVecLogicZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer and/or/xor logicals (ZMM).
|
|
defm WriteVecTest : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer TEST instructions.
|
|
defm WriteVecTestY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (YMM).
|
|
defm WriteVecTestZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer TEST instructions (ZMM).
|
|
defm WriteVecShift : X86SchedWritePair<ReadAfterVecLd>; // Vector integer shifts (default).
|
|
defm WriteVecShiftX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer shifts (XMM).
|
|
defm WriteVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (YMM).
|
|
defm WriteVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer shifts (ZMM).
|
|
defm WriteVecShiftImm : X86SchedWritePair<ReadAfterVecLd>; // Vector integer immediate shifts (default).
|
|
defm WriteVecShiftImmX: X86SchedWritePair<ReadAfterVecXLd>; // Vector integer immediate shifts (XMM).
|
|
defm WriteVecShiftImmY: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (YMM).
|
|
defm WriteVecShiftImmZ: X86SchedWritePair<ReadAfterVecYLd>; // Vector integer immediate shifts (ZMM).
|
|
defm WriteVecIMul : X86SchedWritePair<ReadAfterVecLd>; // Vector integer multiply (default).
|
|
defm WriteVecIMulX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer multiply (XMM).
|
|
defm WriteVecIMulY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (YMM).
|
|
defm WriteVecIMulZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer multiply (ZMM).
|
|
defm WritePMULLD : X86SchedWritePair<ReadAfterVecXLd>; // Vector PMULLD.
|
|
defm WritePMULLDY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (YMM).
|
|
defm WritePMULLDZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PMULLD (ZMM).
|
|
defm WriteShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector shuffles.
|
|
defm WriteShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector shuffles (XMM).
|
|
defm WriteShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (YMM).
|
|
defm WriteShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector shuffles (ZMM).
|
|
defm WriteVarShuffle : X86SchedWritePair<ReadAfterVecLd>; // Vector variable shuffles.
|
|
defm WriteVarShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable shuffles (XMM).
|
|
defm WriteVarShuffleY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (YMM).
|
|
defm WriteVarShuffleZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable shuffles (ZMM).
|
|
defm WriteBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector blends.
|
|
defm WriteBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (YMM).
|
|
defm WriteBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector blends (ZMM).
|
|
defm WriteVarBlend : X86SchedWritePair<ReadAfterVecXLd>; // Vector variable blends.
|
|
defm WriteVarBlendY : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (YMM).
|
|
defm WriteVarBlendZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector variable blends (ZMM).
|
|
defm WritePSADBW : X86SchedWritePair<ReadAfterVecLd>; // Vector PSADBW.
|
|
defm WritePSADBWX : X86SchedWritePair<ReadAfterVecXLd>; // Vector PSADBW (XMM).
|
|
defm WritePSADBWY : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (YMM).
|
|
defm WritePSADBWZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector PSADBW (ZMM).
|
|
defm WriteMPSAD : X86SchedWritePair<ReadAfterVecXLd>; // Vector MPSAD.
|
|
defm WriteMPSADY : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (YMM).
|
|
defm WriteMPSADZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector MPSAD (ZMM).
|
|
defm WritePHMINPOS : X86SchedWritePair<ReadAfterVecXLd>; // Vector PHMINPOS.
|
|
|
|
// Vector insert/extract operations.
|
|
defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element.
|
|
def WriteVecExtract : SchedWrite; // Extract vector element to gpr.
|
|
def WriteVecExtractSt : SchedWrite; // Extract vector element and store.
|
|
|
|
// MOVMSK operations.
|
|
def WriteFMOVMSK : SchedWrite;
|
|
def WriteVecMOVMSK : SchedWrite;
|
|
def WriteVecMOVMSKY : SchedWrite;
|
|
def WriteMMXMOVMSK : SchedWrite;
|
|
|
|
// Conversion between integer and float.
|
|
defm WriteCvtSD2I : X86SchedWritePair<ReadAfterVecLd>; // Double -> Integer.
|
|
defm WriteCvtPD2I : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Integer (XMM).
|
|
defm WriteCvtPD2IY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (YMM).
|
|
defm WriteCvtPD2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (ZMM).
|
|
|
|
defm WriteCvtSS2I : X86SchedWritePair<ReadAfterVecLd>; // Float -> Integer.
|
|
defm WriteCvtPS2I : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Integer (XMM).
|
|
defm WriteCvtPS2IY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (YMM).
|
|
defm WriteCvtPS2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (ZMM).
|
|
|
|
defm WriteCvtI2SD : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Double.
|
|
defm WriteCvtI2PD : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Double (XMM).
|
|
defm WriteCvtI2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (YMM).
|
|
defm WriteCvtI2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (ZMM).
|
|
|
|
defm WriteCvtI2SS : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Float.
|
|
defm WriteCvtI2PS : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Float (XMM).
|
|
defm WriteCvtI2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (YMM).
|
|
defm WriteCvtI2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (ZMM).
|
|
|
|
defm WriteCvtSS2SD : X86SchedWritePair<ReadAfterVecLd>; // Float -> Double size conversion.
|
|
defm WriteCvtPS2PD : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Double size conversion (XMM).
|
|
defm WriteCvtPS2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (YMM).
|
|
defm WriteCvtPS2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (ZMM).
|
|
|
|
defm WriteCvtSD2SS : X86SchedWritePair<ReadAfterVecLd>; // Double -> Float size conversion.
|
|
defm WriteCvtPD2PS : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Float size conversion (XMM).
|
|
defm WriteCvtPD2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (YMM).
|
|
defm WriteCvtPD2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (ZMM).
|
|
|
|
defm WriteCvtPH2PS : X86SchedWritePair<ReadAfterVecXLd>; // Half -> Float size conversion.
|
|
defm WriteCvtPH2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (YMM).
|
|
defm WriteCvtPH2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (ZMM).
|
|
|
|
def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion.
|
|
def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM).
|
|
def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM).
|
|
def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion.
|
|
def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM).
|
|
def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM).
|
|
|
|
// CRC32 instruction.
|
|
defm WriteCRC32 : X86SchedWritePair<ReadAfterLd>;
|
|
|
|
// Strings instructions.
|
|
// Packed Compare Implicit Length Strings, Return Mask
|
|
defm WritePCmpIStrM : X86SchedWritePair<ReadAfterVecXLd>;
|
|
// Packed Compare Explicit Length Strings, Return Mask
|
|
defm WritePCmpEStrM : X86SchedWritePair<ReadAfterVecXLd>;
|
|
// Packed Compare Implicit Length Strings, Return Index
|
|
defm WritePCmpIStrI : X86SchedWritePair<ReadAfterVecXLd>;
|
|
// Packed Compare Explicit Length Strings, Return Index
|
|
defm WritePCmpEStrI : X86SchedWritePair<ReadAfterVecXLd>;
|
|
|
|
// AES instructions.
|
|
defm WriteAESDecEnc : X86SchedWritePair<ReadAfterVecXLd>; // Decryption, encryption.
|
|
defm WriteAESIMC : X86SchedWritePair<ReadAfterVecXLd>; // InvMixColumn.
|
|
defm WriteAESKeyGen : X86SchedWritePair<ReadAfterVecXLd>; // Key Generation.
|
|
|
|
// Carry-less multiplication instructions.
|
|
defm WriteCLMul : X86SchedWritePair<ReadAfterVecXLd>;
|
|
|
|
// EMMS/FEMMS
|
|
def WriteEMMS : SchedWrite;
|
|
|
|
// Load/store MXCSR
|
|
def WriteLDMXCSR : SchedWrite;
|
|
def WriteSTMXCSR : SchedWrite;
|
|
|
|
// Catch-all for expensive system instructions.
|
|
def WriteSystem : SchedWrite;
|
|
|
|
// AVX2.
|
|
defm WriteFShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width vector shuffles.
|
|
defm WriteFVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width variable shuffles.
|
|
defm WriteShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector shuffles.
|
|
defm WriteVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector variable shuffles.
|
|
defm WriteVarVecShift : X86SchedWritePair<ReadAfterVecXLd>; // Variable vector shifts.
|
|
defm WriteVarVecShiftY : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (YMM).
|
|
defm WriteVarVecShiftZ : X86SchedWritePair<ReadAfterVecYLd>; // Variable vector shifts (ZMM).
|
|
|
|
// Old microcoded instructions that nobody use.
|
|
def WriteMicrocoded : SchedWrite;
|
|
|
|
// Fence instructions.
|
|
def WriteFence : SchedWrite;
|
|
|
|
// Nop, not very useful expect it provides a model for nops!
|
|
def WriteNop : SchedWrite;
|
|
|
|
// Move/Load/Store wrappers.
|
|
def WriteFMoveLS
|
|
: X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStore>;
|
|
def WriteFMoveLSX
|
|
: X86SchedWriteMoveLS<WriteFMoveX, WriteFLoadX, WriteFStoreX>;
|
|
def WriteFMoveLSY
|
|
: X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreY>;
|
|
def SchedWriteFMoveLS
|
|
: X86SchedWriteMoveLSWidths<WriteFMoveLS, WriteFMoveLSX,
|
|
WriteFMoveLSY, WriteFMoveLSY>;
|
|
|
|
def WriteFMoveLSNT
|
|
: X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNT>;
|
|
def WriteFMoveLSNTX
|
|
: X86SchedWriteMoveLS<WriteFMove, WriteFLoad, WriteFStoreNTX>;
|
|
def WriteFMoveLSNTY
|
|
: X86SchedWriteMoveLS<WriteFMoveY, WriteFLoadY, WriteFStoreNTY>;
|
|
def SchedWriteFMoveLSNT
|
|
: X86SchedWriteMoveLSWidths<WriteFMoveLSNT, WriteFMoveLSNTX,
|
|
WriteFMoveLSNTY, WriteFMoveLSNTY>;
|
|
|
|
def WriteVecMoveLS
|
|
: X86SchedWriteMoveLS<WriteVecMove, WriteVecLoad, WriteVecStore>;
|
|
def WriteVecMoveLSX
|
|
: X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadX, WriteVecStoreX>;
|
|
def WriteVecMoveLSY
|
|
: X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadY, WriteVecStoreY>;
|
|
def SchedWriteVecMoveLS
|
|
: X86SchedWriteMoveLSWidths<WriteVecMoveLS, WriteVecMoveLSX,
|
|
WriteVecMoveLSY, WriteVecMoveLSY>;
|
|
|
|
def WriteVecMoveLSNT
|
|
: X86SchedWriteMoveLS<WriteVecMove, WriteVecLoadNT, WriteVecStoreNT>;
|
|
def WriteVecMoveLSNTX
|
|
: X86SchedWriteMoveLS<WriteVecMoveX, WriteVecLoadNT, WriteVecStoreNT>;
|
|
def WriteVecMoveLSNTY
|
|
: X86SchedWriteMoveLS<WriteVecMoveY, WriteVecLoadNTY, WriteVecStoreNTY>;
|
|
def SchedWriteVecMoveLSNT
|
|
: X86SchedWriteMoveLSWidths<WriteVecMoveLSNT, WriteVecMoveLSNTX,
|
|
WriteVecMoveLSNTY, WriteVecMoveLSNTY>;
|
|
|
|
// Vector width wrappers.
|
|
def SchedWriteFAdd
|
|
: X86SchedWriteWidths<WriteFAdd, WriteFAddX, WriteFAddY, WriteFAddZ>;
|
|
def SchedWriteFAdd64
|
|
: X86SchedWriteWidths<WriteFAdd64, WriteFAdd64X, WriteFAdd64Y, WriteFAdd64Z>;
|
|
def SchedWriteFHAdd
|
|
: X86SchedWriteWidths<WriteFHAdd, WriteFHAdd, WriteFHAddY, WriteFHAddZ>;
|
|
def SchedWriteFCmp
|
|
: X86SchedWriteWidths<WriteFCmp, WriteFCmpX, WriteFCmpY, WriteFCmpZ>;
|
|
def SchedWriteFCmp64
|
|
: X86SchedWriteWidths<WriteFCmp64, WriteFCmp64X, WriteFCmp64Y, WriteFCmp64Z>;
|
|
def SchedWriteFMul
|
|
: X86SchedWriteWidths<WriteFMul, WriteFMulX, WriteFMulY, WriteFMulZ>;
|
|
def SchedWriteFMul64
|
|
: X86SchedWriteWidths<WriteFMul64, WriteFMul64X, WriteFMul64Y, WriteFMul64Z>;
|
|
def SchedWriteFMA
|
|
: X86SchedWriteWidths<WriteFMA, WriteFMAX, WriteFMAY, WriteFMAZ>;
|
|
def SchedWriteDPPD
|
|
: X86SchedWriteWidths<WriteDPPD, WriteDPPD, WriteDPPD, WriteDPPD>;
|
|
def SchedWriteDPPS
|
|
: X86SchedWriteWidths<WriteDPPS, WriteDPPS, WriteDPPSY, WriteDPPSZ>;
|
|
def SchedWriteFDiv
|
|
: X86SchedWriteWidths<WriteFDiv, WriteFDivX, WriteFDivY, WriteFDivZ>;
|
|
def SchedWriteFDiv64
|
|
: X86SchedWriteWidths<WriteFDiv64, WriteFDiv64X, WriteFDiv64Y, WriteFDiv64Z>;
|
|
def SchedWriteFSqrt
|
|
: X86SchedWriteWidths<WriteFSqrt, WriteFSqrtX,
|
|
WriteFSqrtY, WriteFSqrtZ>;
|
|
def SchedWriteFSqrt64
|
|
: X86SchedWriteWidths<WriteFSqrt64, WriteFSqrt64X,
|
|
WriteFSqrt64Y, WriteFSqrt64Z>;
|
|
def SchedWriteFRcp
|
|
: X86SchedWriteWidths<WriteFRcp, WriteFRcpX, WriteFRcpY, WriteFRcpZ>;
|
|
def SchedWriteFRsqrt
|
|
: X86SchedWriteWidths<WriteFRsqrt, WriteFRsqrtX, WriteFRsqrtY, WriteFRsqrtZ>;
|
|
def SchedWriteFRnd
|
|
: X86SchedWriteWidths<WriteFRnd, WriteFRnd, WriteFRndY, WriteFRndZ>;
|
|
def SchedWriteFLogic
|
|
: X86SchedWriteWidths<WriteFLogic, WriteFLogic, WriteFLogicY, WriteFLogicZ>;
|
|
def SchedWriteFTest
|
|
: X86SchedWriteWidths<WriteFTest, WriteFTest, WriteFTestY, WriteFTestZ>;
|
|
|
|
def SchedWriteFShuffle
|
|
: X86SchedWriteWidths<WriteFShuffle, WriteFShuffle,
|
|
WriteFShuffleY, WriteFShuffleZ>;
|
|
def SchedWriteFVarShuffle
|
|
: X86SchedWriteWidths<WriteFVarShuffle, WriteFVarShuffle,
|
|
WriteFVarShuffleY, WriteFVarShuffleZ>;
|
|
def SchedWriteFBlend
|
|
: X86SchedWriteWidths<WriteFBlend, WriteFBlend, WriteFBlendY, WriteFBlendZ>;
|
|
def SchedWriteFVarBlend
|
|
: X86SchedWriteWidths<WriteFVarBlend, WriteFVarBlend,
|
|
WriteFVarBlendY, WriteFVarBlendZ>;
|
|
|
|
def SchedWriteCvtDQ2PD
|
|
: X86SchedWriteWidths<WriteCvtI2SD, WriteCvtI2PD,
|
|
WriteCvtI2PDY, WriteCvtI2PDZ>;
|
|
def SchedWriteCvtDQ2PS
|
|
: X86SchedWriteWidths<WriteCvtI2SS, WriteCvtI2PS,
|
|
WriteCvtI2PSY, WriteCvtI2PSZ>;
|
|
def SchedWriteCvtPD2DQ
|
|
: X86SchedWriteWidths<WriteCvtSD2I, WriteCvtPD2I,
|
|
WriteCvtPD2IY, WriteCvtPD2IZ>;
|
|
def SchedWriteCvtPS2DQ
|
|
: X86SchedWriteWidths<WriteCvtSS2I, WriteCvtPS2I,
|
|
WriteCvtPS2IY, WriteCvtPS2IZ>;
|
|
def SchedWriteCvtPS2PD
|
|
: X86SchedWriteWidths<WriteCvtSS2SD, WriteCvtPS2PD,
|
|
WriteCvtPS2PDY, WriteCvtPS2PDZ>;
|
|
def SchedWriteCvtPD2PS
|
|
: X86SchedWriteWidths<WriteCvtSD2SS, WriteCvtPD2PS,
|
|
WriteCvtPD2PSY, WriteCvtPD2PSZ>;
|
|
|
|
def SchedWriteVecALU
|
|
: X86SchedWriteWidths<WriteVecALU, WriteVecALUX, WriteVecALUY, WriteVecALUZ>;
|
|
def SchedWritePHAdd
|
|
: X86SchedWriteWidths<WritePHAdd, WritePHAddX, WritePHAddY, WritePHAddZ>;
|
|
def SchedWriteVecLogic
|
|
: X86SchedWriteWidths<WriteVecLogic, WriteVecLogicX,
|
|
WriteVecLogicY, WriteVecLogicZ>;
|
|
def SchedWriteVecTest
|
|
: X86SchedWriteWidths<WriteVecTest, WriteVecTest,
|
|
WriteVecTestY, WriteVecTestZ>;
|
|
def SchedWriteVecShift
|
|
: X86SchedWriteWidths<WriteVecShift, WriteVecShiftX,
|
|
WriteVecShiftY, WriteVecShiftZ>;
|
|
def SchedWriteVecShiftImm
|
|
: X86SchedWriteWidths<WriteVecShiftImm, WriteVecShiftImmX,
|
|
WriteVecShiftImmY, WriteVecShiftImmZ>;
|
|
def SchedWriteVarVecShift
|
|
: X86SchedWriteWidths<WriteVarVecShift, WriteVarVecShift,
|
|
WriteVarVecShiftY, WriteVarVecShiftZ>;
|
|
def SchedWriteVecIMul
|
|
: X86SchedWriteWidths<WriteVecIMul, WriteVecIMulX,
|
|
WriteVecIMulY, WriteVecIMulZ>;
|
|
def SchedWritePMULLD
|
|
: X86SchedWriteWidths<WritePMULLD, WritePMULLD,
|
|
WritePMULLDY, WritePMULLDZ>;
|
|
def SchedWriteMPSAD
|
|
: X86SchedWriteWidths<WriteMPSAD, WriteMPSAD,
|
|
WriteMPSADY, WriteMPSADZ>;
|
|
def SchedWritePSADBW
|
|
: X86SchedWriteWidths<WritePSADBW, WritePSADBWX,
|
|
WritePSADBWY, WritePSADBWZ>;
|
|
|
|
def SchedWriteShuffle
|
|
: X86SchedWriteWidths<WriteShuffle, WriteShuffleX,
|
|
WriteShuffleY, WriteShuffleZ>;
|
|
def SchedWriteVarShuffle
|
|
: X86SchedWriteWidths<WriteVarShuffle, WriteVarShuffleX,
|
|
WriteVarShuffleY, WriteVarShuffleZ>;
|
|
def SchedWriteBlend
|
|
: X86SchedWriteWidths<WriteBlend, WriteBlend, WriteBlendY, WriteBlendZ>;
|
|
def SchedWriteVarBlend
|
|
: X86SchedWriteWidths<WriteVarBlend, WriteVarBlend,
|
|
WriteVarBlendY, WriteVarBlendZ>;
|
|
|
|
// Vector size wrappers.
|
|
def SchedWriteFAddSizes
|
|
: X86SchedWriteSizes<SchedWriteFAdd, SchedWriteFAdd64>;
|
|
def SchedWriteFCmpSizes
|
|
: X86SchedWriteSizes<SchedWriteFCmp, SchedWriteFCmp64>;
|
|
def SchedWriteFMulSizes
|
|
: X86SchedWriteSizes<SchedWriteFMul, SchedWriteFMul64>;
|
|
def SchedWriteFDivSizes
|
|
: X86SchedWriteSizes<SchedWriteFDiv, SchedWriteFDiv64>;
|
|
def SchedWriteFSqrtSizes
|
|
: X86SchedWriteSizes<SchedWriteFSqrt, SchedWriteFSqrt64>;
|
|
def SchedWriteFLogicSizes
|
|
: X86SchedWriteSizes<SchedWriteFLogic, SchedWriteFLogic>;
|
|
def SchedWriteFShuffleSizes
|
|
: X86SchedWriteSizes<SchedWriteFShuffle, SchedWriteFShuffle>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Generic Processor Scheduler Models.
|
|
|
|
// IssueWidth is analogous to the number of decode units. Core and its
|
|
// descendents, including Nehalem and SandyBridge have 4 decoders.
|
|
// Resources beyond the decoder operate on micro-ops and are bufferred
|
|
// so adjacent micro-ops don't directly compete.
|
|
//
|
|
// MicroOpBufferSize > 1 indicates that RAW dependencies can be
|
|
// decoded in the same cycle. The value 32 is a reasonably arbitrary
|
|
// number of in-flight instructions.
|
|
//
|
|
// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
|
|
// indicates high latency opcodes. Alternatively, InstrItinData
|
|
// entries may be included here to define specific operand
|
|
// latencies. Since these latencies are not used for pipeline hazards,
|
|
// they do not need to be exact.
|
|
//
|
|
// The GenericX86Model contains no instruction schedules
|
|
// and disables PostRAScheduler.
|
|
class GenericX86Model : SchedMachineModel {
|
|
let IssueWidth = 4;
|
|
let MicroOpBufferSize = 32;
|
|
let LoadLatency = 4;
|
|
let HighLatency = 10;
|
|
let PostRAScheduler = 0;
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let CompleteModel = 0;
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}
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|
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def GenericModel : GenericX86Model;
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|
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// Define a model with the PostRAScheduler enabled.
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def GenericPostRAModel : GenericX86Model {
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|
let PostRAScheduler = 1;
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|
}
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