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5ad89e1387
Summary: Refactor LiveRangeCalc such that it is now split into two classes The objective is to split all the "register specific" logic away from LiveRangeCalc. The two new classes created are: - LiveRangeCalc - is meant as a generic class to compute and modify live ranges in a generic way. This class should deal only with SlotIndices and VNInfo objects. - LiveIntervalCals - is meant to be equivalent to the old LiveRangeCalc. It computes the liveness virtual registers tracked by a LiveInterval object. With this refactoring LiveRangeCalc can be used to implement tracking of liveness of LiveRanges that represent other things than just registers. Subscribers: MatzeB, qcolombet, mgorny, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76584
455 lines
16 KiB
C++
455 lines
16 KiB
C++
//===- LiveRangeCalc.cpp - Calculate live ranges -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the LiveRangeCalc class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRangeCalc.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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#include <tuple>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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// Reserve an address that indicates a value that is known to be "undef".
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static VNInfo UndefVNI(0xbad, SlotIndex());
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void LiveRangeCalc::resetLiveOutMap() {
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unsigned NumBlocks = MF->getNumBlockIDs();
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Seen.clear();
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Seen.resize(NumBlocks);
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EntryInfos.clear();
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Map.resize(NumBlocks);
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}
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void LiveRangeCalc::reset(const MachineFunction *mf,
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SlotIndexes *SI,
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MachineDominatorTree *MDT,
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VNInfo::Allocator *VNIA) {
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MF = mf;
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MRI = &MF->getRegInfo();
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Indexes = SI;
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DomTree = MDT;
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Alloc = VNIA;
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resetLiveOutMap();
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LiveIn.clear();
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}
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void LiveRangeCalc::updateFromLiveIns() {
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LiveRangeUpdater Updater;
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for (const LiveInBlock &I : LiveIn) {
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if (!I.DomNode)
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continue;
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MachineBasicBlock *MBB = I.DomNode->getBlock();
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assert(I.Value && "No live-in value found");
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(MBB);
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if (I.Kill.isValid())
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// Value is killed inside this block.
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End = I.Kill;
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else {
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// The value is live-through, update LiveOut as well.
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// Defer the Domtree lookup until it is needed.
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assert(Seen.test(MBB->getNumber()));
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Map[MBB] = LiveOutPair(I.Value, nullptr);
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}
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Updater.setDest(&I.LR);
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Updater.add(Start, End, I.Value);
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}
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LiveIn.clear();
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}
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void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
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ArrayRef<SlotIndex> Undefs) {
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assert(Use.isValid() && "Invalid SlotIndex");
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assert(Indexes && "Missing SlotIndexes");
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assert(DomTree && "Missing dominator tree");
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MachineBasicBlock *UseMBB = Indexes->getMBBFromIndex(Use.getPrevSlot());
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assert(UseMBB && "No MBB at Use");
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// Is there a def in the same MBB we can extend?
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auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use);
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if (EP.first != nullptr || EP.second)
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return;
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// Find the single reaching def, or determine if Use is jointly dominated by
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// multiple values, and we may need to create even more phi-defs to preserve
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// VNInfo SSA form. Perform a search for all predecessor blocks where we
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// know the dominating VNInfo.
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if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs))
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return;
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// When there were multiple different values, we may need new PHIs.
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calculateValues();
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}
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// This function is called by a client after using the low-level API to add
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// live-out and live-in blocks. The unique value optimization is not
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// available, SplitEditor::transferValues handles that case directly anyway.
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void LiveRangeCalc::calculateValues() {
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assert(Indexes && "Missing SlotIndexes");
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assert(DomTree && "Missing dominator tree");
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updateSSA();
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updateFromLiveIns();
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}
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bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
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MachineBasicBlock &MBB, BitVector &DefOnEntry,
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BitVector &UndefOnEntry) {
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unsigned BN = MBB.getNumber();
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if (DefOnEntry[BN])
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return true;
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if (UndefOnEntry[BN])
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return false;
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auto MarkDefined = [BN, &DefOnEntry](MachineBasicBlock &B) -> bool {
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for (MachineBasicBlock *S : B.successors())
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DefOnEntry[S->getNumber()] = true;
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DefOnEntry[BN] = true;
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return true;
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};
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SetVector<unsigned> WorkList;
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// Checking if the entry of MBB is reached by some def: add all predecessors
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// that are potentially defined-on-exit to the work list.
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for (MachineBasicBlock *P : MBB.predecessors())
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WorkList.insert(P->getNumber());
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for (unsigned i = 0; i != WorkList.size(); ++i) {
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// Determine if the exit from the block is reached by some def.
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unsigned N = WorkList[i];
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MachineBasicBlock &B = *MF->getBlockNumbered(N);
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if (Seen[N]) {
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const LiveOutPair &LOB = Map[&B];
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if (LOB.first != nullptr && LOB.first != &UndefVNI)
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return MarkDefined(B);
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}
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SlotIndex Begin, End;
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std::tie(Begin, End) = Indexes->getMBBRange(&B);
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// Treat End as not belonging to B.
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// If LR has a segment S that starts at the next block, i.e. [End, ...),
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// std::upper_bound will return the segment following S. Instead,
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// S should be treated as the first segment that does not overlap B.
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LiveRange::iterator UB = std::upper_bound(LR.begin(), LR.end(),
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End.getPrevSlot());
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if (UB != LR.begin()) {
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LiveRange::Segment &Seg = *std::prev(UB);
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if (Seg.end > Begin) {
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// There is a segment that overlaps B. If the range is not explicitly
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// undefined between the end of the segment and the end of the block,
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// treat the block as defined on exit. If it is, go to the next block
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// on the work list.
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if (LR.isUndefIn(Undefs, Seg.end, End))
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continue;
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return MarkDefined(B);
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}
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}
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// No segment overlaps with this block. If this block is not defined on
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// entry, or it undefines the range, do not process its predecessors.
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if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) {
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UndefOnEntry[N] = true;
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continue;
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}
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if (DefOnEntry[N])
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return MarkDefined(B);
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// Still don't know: add all predecessors to the work list.
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for (MachineBasicBlock *P : B.predecessors())
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WorkList.insert(P->getNumber());
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}
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UndefOnEntry[BN] = true;
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return false;
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}
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bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
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SlotIndex Use, unsigned PhysReg,
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ArrayRef<SlotIndex> Undefs) {
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unsigned UseMBBNum = UseMBB.getNumber();
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// Block numbers where LR should be live-in.
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SmallVector<unsigned, 16> WorkList(1, UseMBBNum);
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// Remember if we have seen more than one value.
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bool UniqueVNI = true;
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VNInfo *TheVNI = nullptr;
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bool FoundUndef = false;
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// Using Seen as a visited set, perform a BFS for all reaching defs.
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for (unsigned i = 0; i != WorkList.size(); ++i) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
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#ifndef NDEBUG
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if (MBB->pred_empty()) {
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MBB->getParent()->verify();
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errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo())
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<< " does not have a corresponding definition on every path:\n";
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const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
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if (MI != nullptr)
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errs() << Use << " " << *MI;
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report_fatal_error("Use not jointly dominated by defs.");
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}
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if (Register::isPhysicalRegister(PhysReg) && !MBB->isLiveIn(PhysReg)) {
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MBB->getParent()->verify();
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const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
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errs() << "The register " << printReg(PhysReg, TRI)
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<< " needs to be live in to " << printMBBReference(*MBB)
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<< ", but is missing from the live-in list.\n";
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report_fatal_error("Invalid global physical register");
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}
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#endif
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FoundUndef |= MBB->pred_empty();
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for (MachineBasicBlock *Pred : MBB->predecessors()) {
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// Is this a known live-out block?
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if (Seen.test(Pred->getNumber())) {
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if (VNInfo *VNI = Map[Pred].first) {
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if (TheVNI && TheVNI != VNI)
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UniqueVNI = false;
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TheVNI = VNI;
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}
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continue;
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}
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(Pred);
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// First time we see Pred. Try to determine the live-out value, but set
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// it as null if Pred is live-through with an unknown value.
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auto EP = LR.extendInBlock(Undefs, Start, End);
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VNInfo *VNI = EP.first;
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FoundUndef |= EP.second;
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setLiveOutValue(Pred, EP.second ? &UndefVNI : VNI);
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if (VNI) {
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if (TheVNI && TheVNI != VNI)
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UniqueVNI = false;
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TheVNI = VNI;
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}
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if (VNI || EP.second)
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continue;
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// No, we need a live-in value for Pred as well
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if (Pred != &UseMBB)
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WorkList.push_back(Pred->getNumber());
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else
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// Loopback to UseMBB, so value is really live through.
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Use = SlotIndex();
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}
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}
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LiveIn.clear();
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FoundUndef |= (TheVNI == nullptr || TheVNI == &UndefVNI);
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if (!Undefs.empty() && FoundUndef)
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UniqueVNI = false;
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// Both updateSSA() and LiveRangeUpdater benefit from ordered blocks, but
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// neither require it. Skip the sorting overhead for small updates.
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if (WorkList.size() > 4)
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array_pod_sort(WorkList.begin(), WorkList.end());
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// If a unique reaching def was found, blit in the live ranges immediately.
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if (UniqueVNI) {
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assert(TheVNI != nullptr && TheVNI != &UndefVNI);
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LiveRangeUpdater Updater(&LR);
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for (unsigned BN : WorkList) {
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(BN);
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// Trim the live range in UseMBB.
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if (BN == UseMBBNum && Use.isValid())
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End = Use;
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else
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Map[MF->getBlockNumbered(BN)] = LiveOutPair(TheVNI, nullptr);
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Updater.add(Start, End, TheVNI);
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}
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return true;
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}
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// Prepare the defined/undefined bit vectors.
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EntryInfoMap::iterator Entry;
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bool DidInsert;
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std::tie(Entry, DidInsert) = EntryInfos.insert(
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std::make_pair(&LR, std::make_pair(BitVector(), BitVector())));
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if (DidInsert) {
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// Initialize newly inserted entries.
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unsigned N = MF->getNumBlockIDs();
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Entry->second.first.resize(N);
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Entry->second.second.resize(N);
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}
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BitVector &DefOnEntry = Entry->second.first;
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BitVector &UndefOnEntry = Entry->second.second;
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// Multiple values were found, so transfer the work list to the LiveIn array
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// where UpdateSSA will use it as a work list.
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LiveIn.reserve(WorkList.size());
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for (unsigned BN : WorkList) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(BN);
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if (!Undefs.empty() &&
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!isDefOnEntry(LR, Undefs, *MBB, DefOnEntry, UndefOnEntry))
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continue;
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addLiveInBlock(LR, DomTree->getNode(MBB));
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if (MBB == &UseMBB)
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LiveIn.back().Kill = Use;
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}
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return false;
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}
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// This is essentially the same iterative algorithm that SSAUpdater uses,
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// except we already have a dominator tree, so we don't have to recompute it.
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void LiveRangeCalc::updateSSA() {
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assert(Indexes && "Missing SlotIndexes");
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assert(DomTree && "Missing dominator tree");
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// Interate until convergence.
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bool Changed;
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do {
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Changed = false;
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// Propagate live-out values down the dominator tree, inserting phi-defs
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// when necessary.
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for (LiveInBlock &I : LiveIn) {
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MachineDomTreeNode *Node = I.DomNode;
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// Skip block if the live-in value has already been determined.
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if (!Node)
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continue;
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MachineBasicBlock *MBB = Node->getBlock();
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MachineDomTreeNode *IDom = Node->getIDom();
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LiveOutPair IDomValue;
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// We need a live-in value to a block with no immediate dominator?
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// This is probably an unreachable block that has survived somehow.
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bool needPHI = !IDom || !Seen.test(IDom->getBlock()->getNumber());
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// IDom dominates all of our predecessors, but it may not be their
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// immediate dominator. Check if any of them have live-out values that are
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// properly dominated by IDom. If so, we need a phi-def here.
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if (!needPHI) {
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IDomValue = Map[IDom->getBlock()];
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// Cache the DomTree node that defined the value.
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if (IDomValue.first && IDomValue.first != &UndefVNI &&
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!IDomValue.second) {
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Map[IDom->getBlock()].second = IDomValue.second =
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DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def));
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}
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for (MachineBasicBlock *Pred : MBB->predecessors()) {
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LiveOutPair &Value = Map[Pred];
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if (!Value.first || Value.first == IDomValue.first)
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continue;
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if (Value.first == &UndefVNI) {
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needPHI = true;
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break;
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}
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// Cache the DomTree node that defined the value.
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if (!Value.second)
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Value.second =
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DomTree->getNode(Indexes->getMBBFromIndex(Value.first->def));
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// This predecessor is carrying something other than IDomValue.
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// It could be because IDomValue hasn't propagated yet, or it could be
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// because MBB is in the dominance frontier of that value.
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if (DomTree->dominates(IDom, Value.second)) {
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needPHI = true;
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break;
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}
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}
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}
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// The value may be live-through even if Kill is set, as can happen when
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// we are called from extendRange. In that case LiveOutSeen is true, and
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// LiveOut indicates a foreign or missing value.
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LiveOutPair &LOP = Map[MBB];
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// Create a phi-def if required.
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if (needPHI) {
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Changed = true;
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assert(Alloc && "Need VNInfo allocator to create PHI-defs");
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(MBB);
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LiveRange &LR = I.LR;
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VNInfo *VNI = LR.getNextValue(Start, *Alloc);
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I.Value = VNI;
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// This block is done, we know the final value.
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I.DomNode = nullptr;
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// Add liveness since updateFromLiveIns now skips this node.
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if (I.Kill.isValid()) {
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if (VNI)
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LR.addSegment(LiveInterval::Segment(Start, I.Kill, VNI));
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} else {
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if (VNI)
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LR.addSegment(LiveInterval::Segment(Start, End, VNI));
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LOP = LiveOutPair(VNI, Node);
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}
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} else if (IDomValue.first && IDomValue.first != &UndefVNI) {
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// No phi-def here. Remember incoming value.
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I.Value = IDomValue.first;
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// If the IDomValue is killed in the block, don't propagate through.
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if (I.Kill.isValid())
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continue;
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// Propagate IDomValue if it isn't killed:
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// MBB is live-out and doesn't define its own value.
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if (LOP.first == IDomValue.first)
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continue;
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Changed = true;
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LOP = IDomValue;
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}
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}
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} while (Changed);
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}
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bool LiveRangeCalc::isJointlyDominated(const MachineBasicBlock *MBB,
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ArrayRef<SlotIndex> Defs,
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const SlotIndexes &Indexes) {
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const MachineFunction &MF = *MBB->getParent();
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BitVector DefBlocks(MF.getNumBlockIDs());
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for (SlotIndex I : Defs)
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DefBlocks.set(Indexes.getMBBFromIndex(I)->getNumber());
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SetVector<unsigned> PredQueue;
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PredQueue.insert(MBB->getNumber());
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for (unsigned i = 0; i != PredQueue.size(); ++i) {
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unsigned BN = PredQueue[i];
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if (DefBlocks[BN])
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return true;
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const MachineBasicBlock *B = MF.getBlockNumbered(BN);
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for (const MachineBasicBlock *P : B->predecessors())
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PredQueue.insert(P->getNumber());
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}
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return false;
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}
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