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49f2d14543
Adjust alignment requirements for ds_read/write_b96/b128. GFX9 and onwards allow misaligned access for reads and writes but only if SH_MEM_CONFIG.alignment_mode allows it. UnalignedDSAccess is set on GCN subtargets from GFX9 onward to let us know if we can relax alignment requirements. UnalignedAccessMode acts similary to UnalignedBufferAccess for DS instructions but only from GFX9 onward and is supposed to match alignment_mode. By default alignment of 4 is required. Differential Revision: https://reviews.llvm.org/D82788
131 lines
5.6 KiB
LLVM
131 lines
5.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; There is no dependence between the store and the two loads. So we can combine the loads
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; and the combined load is at the original place of the second load.
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; GCN-LABEL: {{^}}ds_combine_nodep
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
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; GCN-NEXT: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
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define amdgpu_kernel void @ds_combine_nodep(float addrspace(1)* %out, float addrspace(3)* %inptr) {
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%base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)*
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%addr0 = getelementptr i8, i8 addrspace(3)* %base, i32 24
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%tmp0 = bitcast i8 addrspace(3)* %addr0 to float addrspace(3)*
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%vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
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%load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
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%v0 = extractelement <3 x float> %load0, i32 2
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%tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
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%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
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%tmp2 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%vaddrs = bitcast float addrspace(3)* %tmp2 to <2 x float> addrspace(3)*
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store <2 x float> %data, <2 x float> addrspace(3)* %vaddrs, align 4
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%vaddr1 = getelementptr float, float addrspace(3)* %inptr, i32 7
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%v1 = load float, float addrspace(3)* %vaddr1, align 4
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%sum = fadd float %v0, %v1
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store float %sum, float addrspace(1)* %out, align 4
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ret void
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}
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; The store depends on the first load, so we could not move the first load down to combine with
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; the second load directly. However, we can move the store after the combined load.
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; GCN-LABEL: {{^}}ds_combine_WAR
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; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:27
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; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
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define amdgpu_kernel void @ds_combine_WAR(float addrspace(1)* %out, float addrspace(3)* %inptr) {
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%base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)*
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%addr0 = getelementptr i8, i8 addrspace(3)* %base, i32 100
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%tmp0 = bitcast i8 addrspace(3)* %addr0 to float addrspace(3)*
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%vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
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%load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
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%v0 = extractelement <3 x float> %load0, i32 2
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%tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
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%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
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%tmp2 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%vaddrs = bitcast float addrspace(3)* %tmp2 to <2 x float> addrspace(3)*
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store <2 x float> %data, <2 x float> addrspace(3)* %vaddrs, align 4
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%vaddr1 = getelementptr float, float addrspace(3)* %inptr, i32 7
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%v1 = load float, float addrspace(3)* %vaddr1, align 4
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%sum = fadd float %v0, %v1
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store float %sum, float addrspace(1)* %out, align 4
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ret void
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}
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; The second load depends on the store. We can combine the two loads, and the combined load is
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; at the original place of the second load.
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; GCN-LABEL: {{^}}ds_combine_RAW
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
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; GCN-NEXT: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:8 offset1:26
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define amdgpu_kernel void @ds_combine_RAW(float addrspace(1)* %out, float addrspace(3)* %inptr) {
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%base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)*
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%addr0 = getelementptr i8, i8 addrspace(3)* %base, i32 24
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%tmp0 = bitcast i8 addrspace(3)* %addr0 to float addrspace(3)*
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%vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
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%load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
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%v0 = extractelement <3 x float> %load0, i32 2
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%tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
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%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
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%tmp2 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%vaddrs = bitcast float addrspace(3)* %tmp2 to <2 x float> addrspace(3)*
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store <2 x float> %data, <2 x float> addrspace(3)* %vaddrs, align 4
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%vaddr1 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%v1 = load float, float addrspace(3)* %vaddr1, align 4
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%sum = fadd float %v0, %v1
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store float %sum, float addrspace(1)* %out, align 4
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ret void
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}
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; The store depends on the first load, also the second load depends on the store.
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; So we can not combine the two loads.
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; GCN-LABEL: {{^}}ds_combine_WAR_RAW
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; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:108
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; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
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; GCN-NEXT: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:104
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define amdgpu_kernel void @ds_combine_WAR_RAW(float addrspace(1)* %out, float addrspace(3)* %inptr) {
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%base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)*
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%addr0 = getelementptr i8, i8 addrspace(3)* %base, i32 100
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%tmp0 = bitcast i8 addrspace(3)* %addr0 to float addrspace(3)*
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%vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
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%load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
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%v0 = extractelement <3 x float> %load0, i32 2
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%tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
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%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
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%tmp2 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%vaddrs = bitcast float addrspace(3)* %tmp2 to <2 x float> addrspace(3)*
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store <2 x float> %data, <2 x float> addrspace(3)* %vaddrs, align 4
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%vaddr1 = getelementptr float, float addrspace(3)* %inptr, i32 26
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%v1 = load float, float addrspace(3)* %vaddr1, align 4
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%sum = fadd float %v0, %v1
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store float %sum, float addrspace(1)* %out, align 4
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ret void
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}
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