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Summary: This issue from the bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41177 When the two operands for BUILD_VECTOR are same, we will get assert error. llvm::SDValue combineBVOfConsecutiveLoads(llvm::SDNode*, llvm::SelectionDAG&): Assertion `!(InputsAreConsecutiveLoads && InputsAreReverseConsecutive) && "The loads cannot be both consecutive and reverse consecutive."' failed. This error caused by the wrong ElemSIze when calling isConsecutiveLS(). We should use `getScalarType().getStoreSize();` to get the ElemSize instread of `getScalarSizeInBits() / 8`. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D60811 llvm-svn: 358644
13 lines
586 B
LLVM
13 lines
586 B
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s
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; REQUIRES: asserts
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define protected swiftcc void @"$s22LanguageServerProtocol13HoverResponseV8contents5rangeAcA13MarkupContentV_SnyAA8PositionVGSgtcfC"() {
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%1 = load <2 x i64>, <2 x i64>* undef, align 16
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%2 = load i1, i1* undef, align 8
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%3 = insertelement <2 x i1> undef, i1 %2, i32 0
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%4 = shufflevector <2 x i1> %3, <2 x i1> undef, <2 x i32> zeroinitializer
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%5 = select <2 x i1> %4, <2 x i64> zeroinitializer, <2 x i64> %1
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store <2 x i64> %5, <2 x i64>* undef, align 8
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ret void
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}
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