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6705a324ed
The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
55 lines
2.2 KiB
YAML
55 lines
2.2 KiB
YAML
# RUN: llc -mtriple amdgcn -run-pass livevars -run-pass phi-node-elimination -verify-machineinstrs -o - %s | FileCheck %s
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# CHECK-LABEL: phi-cf-test
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# CHECK: bb.0:
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# CHECK: [[COND:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64
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# CHECK: [[IF_SOURCE0:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: [[IF_INPUT_REG:%[0-9]+]]:sreg_64 = S_MOV_B64_term killed [[IF_SOURCE0]], implicit $exec
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# CHECK: bb.1:
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# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY killed [[IF_INPUT_REG]]
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# CHECK: SI_END_CF killed [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: bb.2:
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# CHECK: [[IF_SOURCE1:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: [[IF_INPUT_REG]]:sreg_64 = S_MOV_B64_term killed [[IF_SOURCE1]], implicit $exec
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...
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---
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name: phi-cf-test
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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liveins: $vgpr0
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%5:vgpr_32(s32) = COPY $vgpr0
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%0:sreg_64 = V_CMP_EQ_U32_e64 0, %5(s32), implicit $exec
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%18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%22:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3(0x80000000)
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%24:sreg_64 = PHI %20, %bb.3, %22, %bb.0
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%23:vgpr_32 = PHI %19, %bb.3, %18, %bb.0
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SI_END_CF %24, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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%3:vgpr_32, dead %10:sreg_64 = nsw V_ADD_CO_U32_e64 1, %23, 0, implicit $exec
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bb.3:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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%4:vgpr_32 = PHI %19, %bb.3, %3, %bb.2, %18, %bb.0
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%15:sreg_32_xm0 = S_MOV_B32 61440
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%16:sreg_32_xm0 = S_MOV_B32 -1
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%17:sgpr_128 = REG_SEQUENCE undef %14:sreg_32_xm0, %subreg.sub0, undef %12:sreg_32_xm0, %subreg.sub1, %16, %subreg.sub2, %15, %subreg.sub3
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BUFFER_STORE_DWORD_OFFSET %4, %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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%19:vgpr_32 = COPY %4
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%20:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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...
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