1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 13:11:39 +01:00
llvm-mirror/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
Matt Arsenault 59de807f62 AMDGPU: Start adding MODE register uses to instructions
This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructoins (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
(or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.

Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.
2020-05-27 14:47:00 -04:00

71 lines
2.6 KiB
YAML

# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-dce-in-ra=0 -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
# https://bugs.llvm.org/show_bug.cgi?id=33620
---
# This would assert due to the empty live interval created for %9
# on the last S_NOP with an undef subreg use.
# CHECK-LABEL: name: expecting_non_empty_interval
# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $mode, implicit $exec
# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec
# CHECK: S_NOP 0, implicit %6.sub1
# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
# CHECK-NEXT: S_NOP 0, implicit %8.sub1
# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
name: expecting_non_empty_interval
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
successors: %bb.1
undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec
undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec
bb.1:
S_NOP 0, implicit %2.sub1
S_NOP 0, implicit %0.sub1
S_NOP 0, implicit undef %0.sub0
...
# Similar assert which happens when trying to rematerialize.
# https://bugs.llvm.org/show_bug.cgi?id=33884
---
# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
# CHECK-NOT: MOV
# CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
# CHECK: bb.1:
# CHECK-NEXT: S_NOP 0, implicit %1.sub2
# CHECK-NEXT: S_NOP 0, implicit undef %4.sub0
# CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
# CHECK-NEXT: S_NOP 0, implicit %2.sub2
name: rematerialize_empty_interval_has_reference
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
successors: %bb.1
undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
bb.1:
S_NOP 0, implicit %1.sub2
S_NOP 0, implicit undef %0.sub0
S_NOP 0, implicit %0.sub2
...