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ae86f98e7c
This patch changes the AArch32 crypto instructions (sha2 and aes) to require the specific sha2 or aes features. These features have already been implemented and can be controlled through the command line, but do not have the expected result (i.e. `+noaes` will not disable aes instructions). The crypto feature retains its existing meaning of both sha2 and aes. Several small changes are included due to the knock-on effect this has: - The AArch32 driver has been modified to ensure sha2/aes is correctly set based on arch/cpu/fpu selection and feature ordering. - Crypto extensions are permitted for AArch32 v8-R profile, but not enabled by default. - ACLE feature macros have been updated with the fine grained crypto algorithms. These are also used by AArch64. - Various tests updated due to the change in feature lists and macros. Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D99079
52 lines
2.1 KiB
ArmAsm
52 lines
2.1 KiB
ArmAsm
@ RUN: llvm-mc -triple armv8 -mattr=+neon,+crypto -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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aesd.8 q0, q1
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aese.8 q0, q1
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aesimc.8 q0, q1
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aesmc.8 q0, q1
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@ CHECK: aesd.8 q0, q1 @ encoding: [0x42,0x03,0xb0,0xf3]
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@ CHECK: aese.8 q0, q1 @ encoding: [0x02,0x03,0xb0,0xf3]
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@ CHECK: aesimc.8 q0, q1 @ encoding: [0xc2,0x03,0xb0,0xf3]
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@ CHECK: aesmc.8 q0, q1 @ encoding: [0x82,0x03,0xb0,0xf3]
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@ CHECK-V7: instruction requires: aes armv8
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@ CHECK-V7: instruction requires: aes armv8
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@ CHECK-V7: instruction requires: aes armv8
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@ CHECK-V7: instruction requires: aes armv8
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sha1h.32 q0, q1
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sha1su1.32 q0, q1
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sha256su0.32 q0, q1
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@ CHECK: sha1h.32 q0, q1 @ encoding: [0xc2,0x02,0xb9,0xf3]
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@ CHECK: sha1su1.32 q0, q1 @ encoding: [0x82,0x03,0xba,0xf3]
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@ CHECK: sha256su0.32 q0, q1 @ encoding: [0xc2,0x03,0xba,0xf3]
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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sha1c.32 q0, q1, q2
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sha1m.32 q0, q1, q2
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sha1p.32 q0, q1, q2
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sha1su0.32 q0, q1, q2
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sha256h.32 q0, q1, q2
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sha256h2.32 q0, q1, q2
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sha256su1.32 q0, q1, q2
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@ CHECK: sha1c.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x02,0xf2]
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@ CHECK: sha1m.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xf2]
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@ CHECK: sha1p.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x12,0xf2]
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@ CHECK: sha1su0.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x32,0xf2]
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@ CHECK: sha256h.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x02,0xf3]
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@ CHECK: sha256h2.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x12,0xf3]
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@ CHECK: sha256su1.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xf3]
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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@ CHECK-V7: instruction requires: sha2 armv8
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vmull.p64 q8, d16, d17
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@ CHECK: vmull.p64 q8, d16, d17 @ encoding: [0xa1,0x0e,0xe0,0xf2]
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@ CHECK-V7: instruction requires: aes armv8
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