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0ac8aa21f4
This is the second minimal patch keeping Nios2 target buildable. I'm adding subtarget here and other stuff for frame lowering, instruction, register information methods. I do not add any test cases, as still there are missing parts like DAG selector and assembly printing. I plan to include them into the next patch. Patch by Andrei Grischenko <andrei.l.grischenko@intel.com> Differential Revision: https://reviews.llvm.org/D37256 llvm-svn: 313626
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
//===-- Nios2RegisterInfo.h - Nios2 Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Nios2 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
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#define LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
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#include "Nios2.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "Nios2GenRegisterInfo.inc"
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namespace llvm {
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class Nios2Subtarget;
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class TargetInstrInfo;
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class Type;
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class Nios2RegisterInfo : public Nios2GenRegisterInfo {
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protected:
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const Nios2Subtarget &Subtarget;
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public:
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Nios2RegisterInfo(const Nios2Subtarget &Subtarget);
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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/// Stack Frame Processing Methods
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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/// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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/// Return GPR register class.
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const TargetRegisterClass *intRegClass(unsigned Size) const;
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};
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} // end namespace llvm
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#endif
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