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bea54db865
Add the aarch64[_be]-*-gnu_ilp32 targets to support the GNU ILP32 ABI for AArch64. The needed codegen changes were mostly already implemented in D61259, which added support for the watchOS ILP32 ABI. The main changes are: - Wiring up the new target to enable ILP32 codegen and MC. - ILP32 va_list support. - ILP32 TLSDESC relocation support. There was existing MC support for ELF ILP32 relocations from D25159 which could be enabled by passing "-target-abi ilp32" to llvm-mc. This was changed to check for "gnu_ilp32" in the target triple instead. This shouldn't cause any issues since the existing support was slightly broken: it was generating ELF64 objects instead of the ELF32 object files expected by the GNU ILP32 toolchain. This target has been tested by running the full rustc testsuite on a big-endian ILP32 system based on the GCC ILP32 toolchain. Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D94143
22 lines
780 B
ArmAsm
22 lines
780 B
ArmAsm
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r - | FileCheck -check-prefix=OBJ %s
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// RUN: llvm-mc -triple=aarch64-none-linux-gnu_ilp32 -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r - | FileCheck -check-prefix=OBJ-ILP32 %s
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b somewhere
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bl somewhere
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// OBJ: Relocations [
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// OBJ-NEXT: Section {{.*}} .rela.text {
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// OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0
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// OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0
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// OBJ-NEXT: }
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// OBJ-NEXT: ]
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// OBJ-ILP32: Relocations [
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// OBJ-ILP32-NEXT: Section {{.*}} .rela.text {
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// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_JUMP26 somewhere 0x0
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// OBJ-ILP32-NEXT: 0x4 R_AARCH64_P32_CALL26 somewhere 0x0
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// OBJ-ILP32-NEXT: }
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// OBJ-ILP32-NEXT: ]
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