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https://github.com/RPCS3/llvm-mirror.git
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81afdbc83c
This patch adds support for the next-generation arch14 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch14 as host processor. - Assembler/disassembler support for new instructions. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10304. Note: No currently available Z system supports the arch14 architecture. Once new systems become available, the official system name will be added as supported -march name.
224 lines
5.1 KiB
ArmAsm
224 lines
5.1 KiB
ArmAsm
# For arch14 only.
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# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch14 < %s 2> %t
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# RUN: FileCheck < %t %s
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#CHECK: error: invalid operand
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#CHECK: lbear -1
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#CHECK: error: invalid operand
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#CHECK: lbear 4096
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#CHECK: error: invalid use of indexed addressing
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#CHECK: lbear 0(%r1,%r2)
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lbear -1
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lbear 4096
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lbear 0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: lpswey -524289
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#CHECK: error: invalid operand
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#CHECK: lpswey 524288
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#CHECK: error: invalid use of indexed addressing
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#CHECK: lpswey 0(%r1,%r2)
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lpswey -524289
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lpswey 524288
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lpswey 0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: qpaci -1
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#CHECK: error: invalid operand
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#CHECK: qpaci 4096
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#CHECK: error: invalid use of indexed addressing
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#CHECK: qpaci 0(%r1,%r2)
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qpaci -1
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qpaci 4096
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qpaci 0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: rdp %r0, %r0, %r0, -1
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#CHECK: error: invalid operand
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#CHECK: rdp %r0, %r0, %r0, 16
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rdp %r0, %r0, %r0, -1
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rdp %r0, %r0, %r0, 16
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#CHECK: error: invalid operand
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#CHECK: stbear -1
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#CHECK: error: invalid operand
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#CHECK: stbear 4096
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#CHECK: error: invalid use of indexed addressing
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#CHECK: stbear 0(%r1,%r2)
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stbear -1
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stbear 4096
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stbear 0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: vcfn %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vcfn %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vcfn %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vcfn %v0, %v0, 16, 0
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vcfn %v0, %v0, 0, -1
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vcfn %v0, %v0, 0, 16
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vcfn %v0, %v0, -1, 0
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vcfn %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vclfnl %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vclfnl %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vclfnl %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vclfnl %v0, %v0, 16, 0
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vclfnl %v0, %v0, 0, -1
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vclfnl %v0, %v0, 0, 16
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vclfnl %v0, %v0, -1, 0
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vclfnl %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vclfnh %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vclfnh %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vclfnh %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vclfnh %v0, %v0, 16, 0
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vclfnh %v0, %v0, 0, -1
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vclfnh %v0, %v0, 0, 16
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vclfnh %v0, %v0, -1, 0
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vclfnh %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vcnf %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vcnf %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vcnf %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vcnf %v0, %v0, 16, 0
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vcnf %v0, %v0, 0, -1
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vcnf %v0, %v0, 0, 16
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vcnf %v0, %v0, -1, 0
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vcnf %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vcrnf %v0, %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vcrnf %v0, %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vcrnf %v0, %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vcrnf %v0, %v0, %v0, 16, 0
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vcrnf %v0, %v0, %v0, 0, -1
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vcrnf %v0, %v0, %v0, 0, 16
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vcrnf %v0, %v0, %v0, -1, 0
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vcrnf %v0, %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vclzdp %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vclzdp %v0, %v0, 16
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vclzdp %v0, %v0, -1
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vclzdp %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vcsph %v0, %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vcsph %v0, %v0, %v0, 16
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vcsph %v0, %v0, %v0, -1
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vcsph %v0, %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vpkzr %v0, %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vpkzr %v0, %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vpkzr %v0, %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vpkzr %v0, %v0, %v0, 256, 0
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vpkzr %v0, %v0, %v0, 0, -1
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vpkzr %v0, %v0, %v0, 0, 16
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vpkzr %v0, %v0, %v0, -1, 0
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vpkzr %v0, %v0, %v0, 256, 0
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#CHECK: error: invalid operand
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#CHECK: vschp %v0, %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vschp %v0, %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vschp %v0, %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vschp %v0, %v0, %v0, 16, 0
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vschp %v0, %v0, %v0, 0, -1
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vschp %v0, %v0, %v0, 0, 16
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vschp %v0, %v0, %v0, -1, 0
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vschp %v0, %v0, %v0, 16, 0
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#CHECK: error: invalid operand
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#CHECK: vschsp %v0, %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vschsp %v0, %v0, %v0, 16
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vschsp %v0, %v0, %v0, -1
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vschsp %v0, %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vschdp %v0, %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vschdp %v0, %v0, %v0, 16
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vschdp %v0, %v0, %v0, -1
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vschdp %v0, %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vschxp %v0, %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vschxp %v0, %v0, %v0, 16
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vschxp %v0, %v0, %v0, -1
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vschxp %v0, %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vsrpr %v0, %v0, %v0, 0, -1
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#CHECK: error: invalid operand
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#CHECK: vsrpr %v0, %v0, %v0, 0, 16
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#CHECK: error: invalid operand
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#CHECK: vsrpr %v0, %v0, %v0, -1, 0
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#CHECK: error: invalid operand
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#CHECK: vsrpr %v0, %v0, %v0, 256, 0
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vsrpr %v0, %v0, %v0, 0, -1
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vsrpr %v0, %v0, %v0, 0, 16
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vsrpr %v0, %v0, %v0, -1, 0
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vsrpr %v0, %v0, %v0, 256, 0
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#CHECK: error: invalid operand
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#CHECK: vupkzh %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vupkzh %v0, %v0, 16
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vupkzh %v0, %v0, -1
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vupkzh %v0, %v0, 16
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#CHECK: error: invalid operand
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#CHECK: vupkzl %v0, %v0, -1
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#CHECK: error: invalid operand
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#CHECK: vupkzl %v0, %v0, 16
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vupkzl %v0, %v0, -1
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vupkzl %v0, %v0, 16
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