Eli Friedman 6cf25f5feb [ARM] Implement isExtractSubvectorCheap. ... See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap. Essentially the same considerations apply to ARM. This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles. See https://reviews.llvm.org/D27779 for followup fix. Differential Revision: https://reviews.llvm.org/D27774 llvm-svn: 290198		2016-12-20 20:05:07 +00:00
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AArch64	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
AMDGPU	AMDGPU: Allow 16-bit types in inline asm constraints	2016-12-20 19:06:12 +00:00
ARM	[ARM] Implement isExtractSubvectorCheap.	2016-12-20 20:05:07 +00:00
AVR	[CodeGenPrep] Skip merging empty case blocks	2016-12-16 20:38:39 +00:00
BPF	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
Generic
Hexagon
Inputs
Lanai
Mips
MIR	Move test to correct directory	2016-12-17 02:16:26 +00:00
MSP430
NVPTX	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
PowerPC	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
WinEH
X86	[IR] Remove the DIExpression field from DIGlobalVariable.	2016-12-20 02:09:43 +00:00
XCore