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See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap. Essentially the same considerations apply to ARM. This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles. See https://reviews.llvm.org/D27779 for followup fix. Differential Revision: https://reviews.llvm.org/D27774 llvm-svn: 290198 |
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AVR | ||
BPF | ||
Generic | ||
Hexagon | ||
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Lanai | ||
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MIR | ||
MSP430 | ||
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SPARC | ||
SystemZ | ||
Thumb | ||
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WebAssembly | ||
WinEH | ||
X86 | ||
XCore |