Bjorn Pettersson 6d1749e6c0 [SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero ... When expanding a SMULFIXSAT ISD node (usually originating from a smul.fix.sat intrinsic) we've applied some optimizations for the special case when the scale is zero. The idea has been that it would be cheaper to use an SMULO instruction (if legal) to perform the multiplication and at the same time detect any overflow. And in case of overflow we could use some SELECT:s to replace the result with the saturated min/max value. The only tricky part is to know if we overflowed on the min or max value, i.e. if the product is positive or negative. Unfortunately the implementation has been incorrect as it has looked at the product returned by the SMULO to determine the sign of the product. In case of overflow that product is truncated and won't give us the correct sign bit. This patch is adding an extra XOR of the multiplication operands, which is used to determine the sign of the non truncated product. This patch fixes PR51677. Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D108938 (cherry picked from commit 789f01283d52065b10049b58a3288c4abd1ef351)		2021-08-31 20:59:28 -07:00
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CMakeLists.txt
DAGCombiner.cpp	[DAGCombiner] Stop visitEXTRACT_SUBVECTOR creating illegal BITCASTs post legalisation.	2021-08-16 23:26:32 -07:00
FastISel.cpp	[InstrRef][FastISel] Support emitting DBG_INSTR_REF from fast-isel	2021-07-16 13:56:15 +01:00
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	[SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero	2021-08-31 20:59:28 -07:00
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp	[llvm] Add enum iteration to Sequence	2021-07-21 12:48:53 +00:00
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SelectionDAG.cpp	[SelectionDAG] Support scalable-vector splats in yet more cases	2021-07-26 10:15:08 +01:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp	[AArch64] Legalize MVT::i64x8 in DAG isel lowering	2021-08-02 15:45:58 +01:00
SelectionDAGBuilder.h
SelectionDAGDumper.cpp
SelectionDAGISel.cpp	[DebugInfo][InstrRef] Don't break up ret-sequences on debug-info instrs	2021-07-29 15:08:13 +01:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp
StatepointLowering.h
TargetLowering.cpp	[SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero	2021-08-31 20:59:28 -07:00