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a3de070727
Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
107 lines
4.0 KiB
C++
107 lines
4.0 KiB
C++
//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the x86
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// target library, as used by the LLVM JIT.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86_H
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#define LLVM_LIB_TARGET_X86_X86_H
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class FunctionPass;
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class ImmutablePass;
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class InstructionSelector;
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class PassRegistry;
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class X86RegisterBankInfo;
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class X86Subtarget;
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class X86TargetMachine;
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/// This pass converts a legalized DAG into a X86-specific DAG, ready for
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/// instruction scheduling.
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FunctionPass *createX86ISelDag(X86TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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/// This pass initializes a global base register for PIC on x86-32.
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FunctionPass *createX86GlobalBaseRegPass();
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/// This pass combines multiple accesses to local-dynamic TLS variables so that
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/// the TLS base address for the module is only fetched once per execution path
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/// through the function.
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FunctionPass *createCleanupLocalDynamicTLSPass();
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/// This function returns a pass which converts floating-point register
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/// references and pseudo instructions into floating-point stack references and
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/// physical instructions.
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FunctionPass *createX86FloatingPointStackifierPass();
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/// This pass inserts AVX vzeroupper instructions before each call to avoid
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/// transition penalty between functions encoded with AVX and SSE.
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FunctionPass *createX86IssueVZeroUpperPass();
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/// Return a pass that pads short functions with NOOPs.
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/// This will prevent a stall when returning on the Atom.
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FunctionPass *createX86PadShortFunctions();
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/// Return a pass that selectively replaces certain instructions (like add,
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/// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
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/// instructions, in order to eliminate execution delays in some processors.
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FunctionPass *createX86FixupLEAs();
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/// Return a pass that removes redundant LEA instructions and redundant address
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/// recalculations.
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FunctionPass *createX86OptimizeLEAs();
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/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
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FunctionPass *createX86FixupSetCC();
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/// Return a pass that expands WinAlloca pseudo-instructions.
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FunctionPass *createX86WinAllocaExpander();
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/// Return a pass that optimizes the code-size of x86 call sequences. This is
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/// done by replacing esp-relative movs with pushes.
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FunctionPass *createX86CallFrameOptimization();
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/// Return an IR pass that inserts EH registration stack objects and explicit
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/// EH state updates. This pass must run after EH preparation, which does
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/// Windows-specific but architecture-neutral preparation.
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FunctionPass *createX86WinEHStatePass();
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/// Return a Machine IR pass that expands X86-specific pseudo
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/// instructions into a sequence of actual instructions. This pass
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/// must run after prologue/epilogue insertion and before lowering
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/// the MachineInstr to MC.
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FunctionPass *createX86ExpandPseudoPass();
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/// Return a Machine IR pass that selectively replaces
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/// certain byte and word instructions by equivalent 32 bit instructions,
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/// in order to eliminate partial register usage, false dependences on
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/// the upper portions of registers, and to save code size.
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FunctionPass *createX86FixupBWInsts();
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void initializeFixupBWInstPassPass(PassRegistry &);
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/// This pass replaces EVEX ecnoded of AVX-512 instructiosn by VEX
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/// encoding when possible in order to reduce code size.
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FunctionPass *createX86EvexToVexInsts();
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InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
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X86Subtarget &,
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X86RegisterBankInfo &);
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void initializeEvexToVexInstPassPass(PassRegistry &);
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} // End llvm namespace
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#endif
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