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The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible. vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use. The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above. The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it. This aubmit also includes additional lit tests to cover better HVAs corner cases. Differential Revision: https://reviews.llvm.org/D27392 llvm-svn: 290240
122 lines
4.8 KiB
C++
122 lines
4.8 KiB
C++
//=== X86CallingConv.h - X86 Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the X86 Calling Convention that
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// aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86CALLINGCONV_H
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#define LLVM_LIB_TARGET_X86_X86CALLINGCONV_H
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/IR/CallingConv.h"
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namespace llvm {
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/// When regcall calling convention compiled to 32 bit arch, special treatment
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/// is required for 64 bit masks.
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/// The value should be assigned to two GPRs.
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/// \return true if registers were allocated and false otherwise.
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bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State);
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/// Vectorcall calling convention has special handling for vector types or
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/// HVA for 64 bit arch.
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/// For HVAs shadow registers might be allocated on the first pass
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/// and actual XMM registers are allocated on the second pass.
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/// For vector types, actual XMM registers are allocated on the first pass.
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/// \return true if registers were allocated and false otherwise.
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bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State);
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/// Vectorcall calling convention has special handling for vector types or
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/// HVA for 32 bit arch.
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/// For HVAs actual XMM registers are allocated on the second pass.
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/// For vector types, actual XMM registers are allocated on the first pass.
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/// \return true if registers were allocated and false otherwise.
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bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State);
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inline bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &,
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CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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CCState &) {
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llvm_unreachable("The AnyReg calling convention is only supported by the " \
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"stackmap and patchpoint intrinsics.");
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// gracefully fallback to X86 C calling convention on Release builds.
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return false;
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}
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inline bool CC_X86_32_MCUInReg(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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// This is similar to CCAssignToReg<[EAX, EDX, ECX]>, but makes sure
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// not to split i64 and double between a register and stack
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static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX};
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static const unsigned NumRegs = sizeof(RegList)/sizeof(RegList[0]);
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SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
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// If this is the first part of an double/i64/i128, or if we're already
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// in the middle of a split, add to the pending list. If this is not
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// the end of the split, return, otherwise go on to process the pending
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// list
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if (ArgFlags.isSplit() || !PendingMembers.empty()) {
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PendingMembers.push_back(
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CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
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if (!ArgFlags.isSplitEnd())
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return true;
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}
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// If there are no pending members, we are not in the middle of a split,
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// so do the usual inreg stuff.
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if (PendingMembers.empty()) {
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if (unsigned Reg = State.AllocateReg(RegList)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true;
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}
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return false;
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}
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assert(ArgFlags.isSplitEnd());
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// We now have the entire original argument in PendingMembers, so decide
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// whether to use registers or the stack.
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// Per the MCU ABI:
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// a) To use registers, we need to have enough of them free to contain
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// the entire argument.
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// b) We never want to use more than 2 registers for a single argument.
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unsigned FirstFree = State.getFirstUnallocated(RegList);
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bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree);
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for (auto &It : PendingMembers) {
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if (UseRegs)
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It.convertToReg(State.AllocateReg(RegList[FirstFree++]));
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else
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It.convertToMem(State.AllocateStack(4, 4));
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State.addLoc(It);
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}
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PendingMembers.clear();
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return true;
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}
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} // End llvm namespace
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#endif
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