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8ecd0ea322
Some register-register instructions can be encoded in 2 different ways, this happens when 2 register operands can be folded (separately). For example if we look at the MOV8rr and MOV8rr_REV, both instructions perform exactly the same operation, but are encoded differently. Here is the relevant information about these instructions from Intel's 64-ia-32-architectures-software-developer-manual: Opcode Instruction Op/En 64-Bit Mode Compat/Leg Mode Description 8A /r MOV r8,r/m8 RM Valid Valid Move r/m8 to r8. 88 /r MOV r/m8,r8 MR Valid Valid Move r8 to r/m8. Here we can see that in order to enable the folding of the output and input registers, we had to define 2 "encodings", and as a result we got 2 move 8-bit register-register instructions. In the X86 backend, we define both of these instructions, usually one has a regular name (MOV8rr) while the other has "_REV" suffix (MOV8rr_REV), must be marked with isCodeGenOnly flag and is not emitted from CodeGen. Automatically generating the memory folding tables relies on matching encodings of instructions, but in these cases where we want to map both memory forms of the mov 8-bit (MOV8rm & MOV8mr) to MOV8rr (not to MOV8rr_REV) we have to somehow point from the MOV8rr_REV to the "regular" appropriate instruction which in this case is MOV8rr. This field enable this "pointing" mechanism - which is used in the TableGen backend for generating memory folding tables. Differential Revision: https://reviews.llvm.org/D32683 llvm-svn: 304087
453 lines
23 KiB
TableGen
453 lines
23 KiB
TableGen
//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes FMA (Fused Multiply-Add) instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FMA3 - Intel 3 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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// For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined
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// below, both the register and memory variants are commutable.
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// For the register form the commutable operands are 1, 2 and 3.
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// For the memory variant the folded operand must be in 3. Thus,
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// in that case, only the operands 1 and 2 can be swapped.
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// Commuting some of operands may require the opcode change.
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// FMA*213*:
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// operands 1 and 2 (memory & register forms): *213* --> *213*(no changes);
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// operands 1 and 3 (register forms only): *213* --> *231*;
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// operands 2 and 3 (register forms only): *213* --> *132*.
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// FMA*132*:
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// operands 1 and 2 (memory & register forms): *132* --> *231*;
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// operands 1 and 3 (register forms only): *132* --> *132*(no changes);
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// operands 2 and 3 (register forms only): *132* --> *213*.
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// FMA*231*:
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// operands 1 and 2 (memory & register forms): *231* --> *132*;
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// operands 1 and 3 (register forms only): *231* --> *213*;
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// operands 2 and 3 (register forms only): *231* --> *231*(no changes).
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let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in
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multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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PatFrag MemFrag128, PatFrag MemFrag256,
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ValueType OpVT128, ValueType OpVT256,
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SDPatternOperator Op = null_frag> {
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2,
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VR128:$src1, VR128:$src3)))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
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(MemFrag128 addr:$src3))))]>;
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def Yr : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
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VR256:$src3)))]>, VEX_L;
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let mayLoad = 1 in
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def Ym : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst,
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(OpVT256 (Op VR256:$src2, VR256:$src1,
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(MemFrag256 addr:$src3))))]>, VEX_L;
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}
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multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpcodeStr, string PackTy, string Suff,
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PatFrag MemFrag128, PatFrag MemFrag256,
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SDNode Op, ValueType OpTy128, ValueType OpTy256> {
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defm NAME#213#Suff : fma3p_rm<opc213,
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!strconcat(OpcodeStr, "213", PackTy),
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MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
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defm NAME#132#Suff : fma3p_rm<opc132,
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!strconcat(OpcodeStr, "132", PackTy),
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MemFrag128, MemFrag256, OpTy128, OpTy256>;
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defm NAME#231#Suff : fma3p_rm<opc231,
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!strconcat(OpcodeStr, "231", PackTy),
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MemFrag128, MemFrag256, OpTy128, OpTy256>;
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}
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// Fused Multiply-Add
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS",
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loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32>;
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defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS",
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loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32>;
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defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS",
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loadv4f32, loadv8f32, X86Fmaddsub,
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v4f32, v8f32>;
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defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS",
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loadv4f32, loadv8f32, X86Fmsubadd,
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v4f32, v8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD",
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loadv2f64, loadv4f64, X86Fmadd, v2f64,
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v4f64>, VEX_W;
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defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD",
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loadv2f64, loadv4f64, X86Fmsub, v2f64,
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v4f64>, VEX_W;
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defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD",
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loadv2f64, loadv4f64, X86Fmaddsub,
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v2f64, v4f64>, VEX_W;
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defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD",
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loadv2f64, loadv4f64, X86Fmsubadd,
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v2f64, v4f64>, VEX_W;
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}
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// Fused Negative Multiply-Add
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let ExeDomain = SSEPackedSingle in {
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defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32,
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loadv8f32, X86Fnmadd, v4f32, v8f32>;
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defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32,
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loadv8f32, X86Fnmsub, v4f32, v8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64,
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loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
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defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64,
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loadv4f64, X86Fnmsub, v2f64, v4f64>, VEX_W;
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}
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// All source register operands of FMA opcodes defined in fma3s_rm multiclass
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// can be commuted. In many cases such commute transformation requres an opcode
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// adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
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// would require an opcode change to FMA*231:
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// FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
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// -->
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// FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;
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// Please see more detailed comment at the very beginning of the section
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// defining FMA3 opcodes above.
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let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr,
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X86MemOperand x86memop, RegisterClass RC,
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SDPatternOperator OpNode = null_frag> {
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
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}
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// These FMA*_Int instructions are defined specially for being used when
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// the scalar FMA intrinsics are lowered to machine instructions, and in that
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// sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc.
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// instructions.
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//
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// All of the FMA*_Int opcodes are defined as commutable here.
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// Commuting the 2nd and 3rd source register operands of FMAs is quite trivial
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// and the corresponding optimizations have been developed.
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// Commuting the 1st operand of FMA*_Int requires some additional analysis,
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// the commute optimization is legal only if all users of FMA*_Int use only
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// the lowest element of the FMA*_Int instruction. Even though such analysis
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// may be not implemented yet we allow the routines doing the actual commute
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// transformation to decide if one or another instruction is commutable or not.
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let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1,
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hasSideEffects = 0 in
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multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr,
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Operand memopr, RegisterClass RC> {
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def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[]>;
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let mayLoad = 1 in
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def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, memopr:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[]>;
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}
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multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, string PackTy, string Suff,
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SDNode OpNode, RegisterClass RC,
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X86MemOperand x86memop> {
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let Predicates = [HasFMA, NoAVX512] in {
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defm NAME#132#Suff : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy),
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x86memop, RC>;
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defm NAME#213#Suff : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy),
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x86memop, RC, OpNode>;
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defm NAME#231#Suff : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy),
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x86memop, RC>;
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}
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}
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// The FMA 213 form is created for lowering of scalar FMA intrinscis
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// to machine instructions.
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// The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands
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// of FMA 213 form.
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// The FMA 231 form can be get only by commuting the 1st operand of 213 or 132
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// forms and is possible only after special analysis of all uses of the initial
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// instruction. Such analysis do not exist yet and thus introducing the 231
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// form of FMA*_Int instructions is done using an optimistic assumption that
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// such analysis will be implemented eventually.
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multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, string PackTy, string Suff,
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RegisterClass RC, Operand memop> {
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defm NAME#132#Suff : fma3s_rm_int<opc132, !strconcat(OpStr, "132", PackTy),
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memop, RC>;
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defm NAME#213#Suff : fma3s_rm_int<opc213, !strconcat(OpStr, "213", PackTy),
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memop, RC>;
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defm NAME#231#Suff : fma3s_rm_int<opc231, !strconcat(OpStr, "231", PackTy),
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memop, RC>;
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}
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multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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SDNode OpNode> {
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let ExeDomain = SSEPackedSingle in
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defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", OpNode,
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FR32, f32mem>,
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fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", "SS",
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VR128, ssmem>;
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let ExeDomain = SSEPackedDouble in
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defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "SD", OpNode,
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FR64, f64mem>,
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fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", "SD",
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VR128, sdmem>, VEX_W;
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// These patterns use the 123 ordering, instead of 213, even though
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// they match the intrinsic to the 213 version of the instruction.
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// This is because src1 is tied to dest, and the scalar intrinsics
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// require the pass-through values to come from the first source
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// operand, not the second.
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let Predicates = [HasFMA] in {
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def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
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(COPY_TO_REGCLASS(!cast<Instruction>(NAME#"213SSr_Int")
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$src1, $src2, $src3), VR128)>;
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def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
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(COPY_TO_REGCLASS(!cast<Instruction>(NAME#"213SDr_Int")
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$src1, $src2, $src3), VR128)>;
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}
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}
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defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
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int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
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defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
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int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
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defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
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int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
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defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
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int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
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//===----------------------------------------------------------------------===//
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// FMA4 - AMD 4 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
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PatFrag mem_frag> {
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let isCommutable = 1 in
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def rr : FMA4<opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG;
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def rm : FMA4<opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3)))]>, VEX_W, VEX_LIG;
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def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst,
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(OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
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VEX_LIG, FoldGenData<NAME#rr>;
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}
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multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic Int> {
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let isCodeGenOnly = 1 in {
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def rr_Int : FMA4<opc, MRMSrcRegOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG;
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def rm_Int : FMA4<opc, MRMSrcMemOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
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mem_cpat:$src3))]>, VEX_W, VEX_LIG;
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def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
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let hasSideEffects = 0 in
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def rr_Int_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[]>, VEX_LIG, FoldGenData<NAME#rr_Int>;
|
|
} // isCodeGenOnly = 1
|
|
}
|
|
|
|
multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
ValueType OpVT128, ValueType OpVT256,
|
|
PatFrag ld_frag128, PatFrag ld_frag256> {
|
|
let isCommutable = 1 in
|
|
def rr : FMA4<opc, MRMSrcRegOp4, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
|
|
VEX_W;
|
|
def rm : FMA4<opc, MRMSrcMemOp4, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
|
|
(ld_frag128 addr:$src3)))]>, VEX_W;
|
|
def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, f128mem:$src2, VR128:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
|
|
let isCommutable = 1 in
|
|
def Yrr : FMA4<opc, MRMSrcRegOp4, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst,
|
|
(OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
|
|
VEX_W, VEX_L;
|
|
def Yrm : FMA4<opc, MRMSrcMemOp4, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
|
|
(ld_frag256 addr:$src3)))]>, VEX_W, VEX_L;
|
|
def Ymr : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
|
|
(ins VR256:$src1, f256mem:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst, (OpNode VR256:$src1,
|
|
(ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
|
|
// For disassembler
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
|
|
def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
|
|
FoldGenData<NAME#rr>;
|
|
def Yrr_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
|
|
VEX_L, FoldGenData<NAME#Yrr>;
|
|
} // isCodeGenOnly = 1
|
|
}
|
|
|
|
let ExeDomain = SSEPackedSingle in {
|
|
// Scalar Instructions
|
|
defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
|
|
fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
|
|
int_x86_fma_vfmadd_ss>;
|
|
defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
|
|
fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
|
|
int_x86_fma_vfmsub_ss>;
|
|
defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
|
|
X86Fnmadd, loadf32>,
|
|
fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
|
|
int_x86_fma_vfnmadd_ss>;
|
|
defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
|
|
X86Fnmsub, loadf32>,
|
|
fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
|
|
int_x86_fma_vfnmsub_ss>;
|
|
// Packed Instructions
|
|
defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
|
|
loadv4f32, loadv8f32>;
|
|
}
|
|
|
|
let ExeDomain = SSEPackedDouble in {
|
|
// Scalar Instructions
|
|
defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
|
|
fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
|
|
int_x86_fma_vfmadd_sd>;
|
|
defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
|
|
fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
|
|
int_x86_fma_vfmsub_sd>;
|
|
defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
|
|
X86Fnmadd, loadf64>,
|
|
fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
|
|
int_x86_fma_vfnmadd_sd>;
|
|
defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
|
|
X86Fnmsub, loadf64>,
|
|
fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
|
|
int_x86_fma_vfnmsub_sd>;
|
|
// Packed Instructions
|
|
defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
|
|
loadv2f64, loadv4f64>;
|
|
}
|
|
|