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110 lines
3.1 KiB
LLVM
110 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; ModuleID = 'test/Transforms/InstCombine/add4.ll'
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source_filename = "test/Transforms/InstCombine/add4.ll"
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define i64 @match_unsigned(i64 %x) {
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; CHECK-LABEL: @match_unsigned(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
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; CHECK-NEXT: ret i64 [[UREM]]
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;
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bb:
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%tmp = urem i64 %x, 299
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%tmp1 = udiv i64 %x, 299
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%tmp2 = urem i64 %tmp1, 64
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%tmp3 = mul i64 %tmp2, 299
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%tmp4 = add i64 %tmp, %tmp3
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ret i64 %tmp4
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}
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define i64 @match_andAsRem_lshrAsDiv_shlAsMul(i64 %x) {
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; CHECK-LABEL: @match_andAsRem_lshrAsDiv_shlAsMul(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
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; CHECK-NEXT: ret i64 [[UREM]]
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;
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bb:
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%tmp = and i64 %x, 63
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%tmp1 = lshr i64 %x, 6
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%tmp2 = urem i64 %tmp1, 9
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%tmp3 = shl i64 %tmp2, 6
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%tmp4 = add i64 %tmp, %tmp3
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ret i64 %tmp4
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}
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define i64 @match_signed(i64 %x) {
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; CHECK-LABEL: @match_signed(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[SREM1:%.*]] = srem i64 [[X:%.*]], 172224
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; CHECK-NEXT: ret i64 [[SREM1]]
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;
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bb:
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%tmp = srem i64 %x, 299
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%tmp1 = sdiv i64 %x, 299
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%tmp2 = srem i64 %tmp1, 64
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%tmp3 = sdiv i64 %x, 19136
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%tmp4 = srem i64 %tmp3, 9
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%tmp5 = mul i64 %tmp2, 299
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%tmp6 = add i64 %tmp, %tmp5
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%tmp7 = mul i64 %tmp4, 19136
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%tmp8 = add i64 %tmp6, %tmp7
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ret i64 %tmp8
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}
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define i64 @not_match_inconsistent_signs(i64 %x) {
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; CHECK-LABEL: @not_match_inconsistent_signs(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = urem i64 [[X:%.*]], 299
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; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[X]], 299
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; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 63
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; CHECK-NEXT: [[TMP3:%.*]] = mul nuw nsw i64 [[TMP2]], 299
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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bb:
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%tmp = urem i64 %x, 299
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%tmp1 = sdiv i64 %x, 299
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%tmp2 = urem i64 %tmp1, 64
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%tmp3 = mul i64 %tmp2, 299
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%tmp4 = add i64 %tmp, %tmp3
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ret i64 %tmp4
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}
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define i64 @not_match_inconsistent_values(i64 %x) {
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; CHECK-LABEL: @not_match_inconsistent_values(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = urem i64 [[X:%.*]], 299
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; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[X]], 29
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; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 63
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; CHECK-NEXT: [[TMP3:%.*]] = mul nuw nsw i64 [[TMP2]], 299
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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bb:
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%tmp = urem i64 %x, 299
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%tmp1 = udiv i64 %x, 29
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%tmp2 = urem i64 %tmp1, 64
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%tmp3 = mul i64 %tmp2, 299
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%tmp4 = add i64 %tmp, %tmp3
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ret i64 %tmp4
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}
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define i32 @not_match_overflow(i32 %x) {
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; CHECK-LABEL: @not_match_overflow(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = urem i32 [[X:%.*]], 299
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; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[X]], 299
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; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[X]], [[TMP0]]
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; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
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bb:
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%tmp = urem i32 %x, 299
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%tmp1 = udiv i32 %x,299
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%tmp2 = urem i32 %tmp1, 147483647
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%tmp3 = mul i32 %tmp2, 299
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%tmp4 = add i32 %tmp, %tmp3
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ret i32 %tmp4
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}
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