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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
25 lines
1008 B
LLVM
25 lines
1008 B
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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; load a v2i32 value from the global address space.
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; EG-CHECK: {{^}}load_v2i32:
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; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0
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; SI-CHECK: {{^}}load_v2i32:
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; SI-CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}]
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define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%a = load <2 x i32> addrspace(1) * %in
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store <2 x i32> %a, <2 x i32> addrspace(1)* %out
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ret void
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}
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; load a v4i32 value from the global address space.
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; EG-CHECK: {{^}}load_v4i32:
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; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
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; SI-CHECK: {{^}}load_v4i32:
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; SI-CHECK: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}]
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define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%a = load <4 x i32> addrspace(1) * %in
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store <4 x i32> %a, <4 x i32> addrspace(1)* %out
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ret void
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}
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