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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
57 lines
1.7 KiB
LLVM
57 lines
1.7 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}rotl_i32:
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; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
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; R600-NEXT: 32
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; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
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; SI: s_sub_i32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}}
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; SI: v_mov_b32_e32 [[VDST:v[0-9]+]], [[SDST]]
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; SI: v_alignbit_b32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]]
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define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = shl i32 %x, %y
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%1 = sub i32 32, %y
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%2 = lshr i32 %x, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: {{^}}rotl_v2i32:
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; SI-DAG: s_sub_i32
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; SI-DAG: s_sub_i32
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; SI-DAG: v_alignbit_b32
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; SI-DAG: v_alignbit_b32
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; SI: s_endpgm
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define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
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entry:
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%0 = shl <2 x i32> %x, %y
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%1 = sub <2 x i32> <i32 32, i32 32>, %y
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%2 = lshr <2 x i32> %x, %1
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%3 = or <2 x i32> %0, %2
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store <2 x i32> %3, <2 x i32> addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: {{^}}rotl_v4i32:
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; SI-DAG: s_sub_i32
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; SI-DAG: v_alignbit_b32
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; SI-DAG: s_sub_i32
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; SI-DAG: v_alignbit_b32
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; SI-DAG: s_sub_i32
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; SI-DAG: v_alignbit_b32
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; SI-DAG: s_sub_i32
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; SI-DAG: v_alignbit_b32
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; SI: s_endpgm
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define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
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entry:
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%0 = shl <4 x i32> %x, %y
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%1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
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%2 = lshr <4 x i32> %x, %1
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%3 = or <4 x i32> %0, %2
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store <4 x i32> %3, <4 x i32> addrspace(1)* %in
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ret void
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}
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