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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: {{^}}test:
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; SI-CHECK: {{^}}test:
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; SI-CHECK: s_mov_b32 [[ZERO:s[0-9]]], 0{{$}}
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; SI-CHECK: v_mov_b32_e32 v[[V_ZERO:[0-9]]], [[ZERO]]
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; SI-CHECK: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}}
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define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = mul i32 %a, %b
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%1 = add i32 %0, %c
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%2 = zext i32 %1 to i64
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store i64 %2, i64 addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: {{^}}testi1toi32:
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; SI-CHECK: v_cndmask_b32
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define void @testi1toi32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = icmp eq i32 %a, %b
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%1 = zext i1 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: {{^}}zext_i1_to_i64:
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; SI-CHECK: v_cmp_eq_i32
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; SI-CHECK: v_cndmask_b32
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; SI-CHECK: s_mov_b32 s{{[0-9]+}}, 0
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define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%ext = zext i1 %cmp to i64
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store i64 %ext, i64 addrspace(1)* %out, align 8
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ret void
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}
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