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llvm-mirror/test/MC/VE/CVTSQ.s
Kazushi (Jam) Marukawa 1ac9e25624 [VE] Support convert instructions in MC layer
Summary:
Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions.  Add regression tests for
them and other convert instructions of asmparser, mccodeemitter, and
disassembler.  In order to add those instructions, support RD operands
in asmparser, mccodeemitter, and disassembler.

Differential Revision: https://reviews.llvm.org/D81536
2020-06-10 12:22:33 +02:00

21 lines
721 B
ArmAsm

# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: cvt.s.q %s11, %s12
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x8b,0x1f]
cvt.s.q %s11, %s12
# CHECK-INST: cvt.s.q %s11, 63
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x8b,0x1f]
cvt.s.q %s11, 63
# CHECK-INST: cvt.s.q %s11, -64
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x40,0x8b,0x1f]
cvt.s.q %s11, -64
# CHECK-INST: cvt.s.q %s11, -1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x7f,0x8b,0x1f]
cvt.s.q %s11, -1