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1bb14916f2
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
62 lines
1.7 KiB
LLVM
62 lines
1.7 KiB
LLVM
; RUN: opt -codegenprepare -mtriple=arm64_32-apple-ios %s -S -o - | FileCheck %s
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define void @test_simple_sink(i1* %base, i64 %offset) {
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; CHECK-LABEL: @test_simple_sink
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; CHECK: next:
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; CHECK: [[BASE8:%.*]] = bitcast i1* %base to i8*
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; CHECK: [[ADDR8:%.*]] = getelementptr i8, i8* [[BASE8]], i64 %offset
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; CHECK: [[ADDR:%.*]] = bitcast i8* [[ADDR8]] to i1*
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; CHECK: load volatile i1, i1* [[ADDR]]
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%addr = getelementptr i1, i1* %base, i64 %offset
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%tst = load i1, i1* %addr
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br i1 %tst, label %next, label %end
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next:
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load volatile i1, i1* %addr
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ret void
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end:
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ret void
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}
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define void @test_inbounds_sink(i1* %base, i64 %offset) {
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; CHECK-LABEL: @test_inbounds_sink
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; CHECK: next:
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; CHECK: [[BASE8:%.*]] = bitcast i1* %base to i8*
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; CHECK: [[ADDR8:%.*]] = getelementptr inbounds i8, i8* [[BASE8]], i64 %offset
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; CHECK: [[ADDR:%.*]] = bitcast i8* [[ADDR8]] to i1*
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; CHECK: load volatile i1, i1* [[ADDR]]
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%addr = getelementptr inbounds i1, i1* %base, i64 %offset
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%tst = load i1, i1* %addr
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br i1 %tst, label %next, label %end
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next:
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load volatile i1, i1* %addr
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ret void
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end:
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ret void
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}
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; No address derived via an add can be guaranteed inbounds
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define void @test_add_sink(i1* %base, i64 %offset) {
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; CHECK-LABEL: @test_add_sink
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; CHECK: next:
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; CHECK: [[BASE8:%.*]] = bitcast i1* %base to i8*
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; CHECK: [[ADDR8:%.*]] = getelementptr i8, i8* [[BASE8]], i64 %offset
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; CHECK: [[ADDR:%.*]] = bitcast i8* [[ADDR8]] to i1*
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; CHECK: load volatile i1, i1* [[ADDR]]
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%base64 = ptrtoint i1* %base to i64
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%addr64 = add nsw nuw i64 %base64, %offset
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%addr = inttoptr i64 %addr64 to i1*
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%tst = load i1, i1* %addr
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br i1 %tst, label %next, label %end
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next:
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load volatile i1, i1* %addr
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ret void
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end:
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ret void
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}
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