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edcf928591
Summary: This implements the lowering of the X constraint on AArch64. The default behaviour of the X constraint lowering is to restrict it to "f". This is a problem because the "f" constraint is not implemented on AArch64 and would be too restrictive anyway. Therefore, the AArch64 hook will lower this to "w" (if the operand is a floating point or vector) or "r" otherwise. The implementation is similar with the one added for ARM (r267411). This is the AArch64 side of the fix for http://llvm.org/PR26493 Reviewers: rengolin Subscribers: aemerson, rengolin, llvm-commits, t.p.northover Differential Revision: http://reviews.llvm.org/D19967 llvm-svn: 268907
153 lines
4.5 KiB
LLVM
153 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o - | FileCheck %s
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; The following functions test the use case where an X constraint is used to
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; add a dependency between an assembly instruction (vmsr in this case) and
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; another instruction. In each function, we use a different type for the
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; X constraint argument.
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;
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; We can something similar from the following C code:
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; double f1(double f, int pscr_value) {
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; asm volatile("msr fpsr,%1" : "=X" ((f)): "r" (pscr_value));
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; return f+f;
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; }
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; CHECK-LABEL: f1
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; CHECK: msr FPSR
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; CHECK: fadd d
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define double @f1(double %f, i32 %pscr_value) {
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entry:
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%f.addr = alloca double, align 8
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store double %f, double* %f.addr, align 8
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call void asm sideeffect "msr fpsr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwind
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%0 = load double, double* %f.addr, align 8
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%add = fadd double %0, %0
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ret double %add
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}
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; int f2(int f, int pscr_value) {
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; asm volatile("msr fpsr,$1" : "=X" ((f)): "r" (pscr_value));
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; return f*f;
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; }
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; CHECK-LABEL: f2
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; CHECK: msr FPSR
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; CHECK: mul
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define i32 @f2(i32 %f, i32 %pscr_value) {
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entry:
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%f.addr = alloca i32, align 4
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store i32 %f, i32* %f.addr, align 4
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call void asm sideeffect "msr fpsr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
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%0 = load i32, i32* %f.addr, align 4
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%mul = mul i32 %0, %0
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ret i32 %mul
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}
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; typedef signed char int8_t;
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; typedef __attribute__((neon_vector_type(8))) int8_t int8x8_t;
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; void f3 (void)
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; {
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; int8x8_t vector_res_int8x8;
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; unsigned int fpscr;
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; asm volatile ("msr fpsr,$1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
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; return vector_res_int8x8 * vector_res_int8x8;
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; }
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; CHECK-LABEL: f3
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; CHECK: msr FPSR
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; CHECK: mul
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define <8 x i8> @f3() {
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entry:
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%vector_res_int8x8 = alloca <8 x i8>, align 8
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%0 = getelementptr inbounds <8 x i8>, <8 x i8>* %vector_res_int8x8, i32 0, i32 0
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call void asm sideeffect "msr fpsr,$1", "=*X,r"(<8 x i8>* nonnull %vector_res_int8x8, i32 undef) nounwind
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%1 = load <8 x i8>, <8 x i8>* %vector_res_int8x8, align 8
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%mul = mul <8 x i8> %1, %1
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ret <8 x i8> %mul
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}
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; We can emit integer constants.
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; We can get this from:
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; void f() {
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; int x = 2;
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; asm volatile ("add x0, x0, %0" : : "X" (x));
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; }
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;
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; CHECK-LABEL: f4
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; CHECK: add x0, x0, #2
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define void @f4() {
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entry:
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tail call void asm sideeffect "add x0, x0, $0", "X"(i32 2)
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ret void
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}
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; We can emit function labels. This is equivalent to the following C code:
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; void f(void) {
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; void (*x)(void) = &foo;
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; asm volatile ("bl %0" : : "X" (x));
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; }
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; CHECK-LABEL: f5
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; CHECK: bl f4
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define void @f5() {
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entry:
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tail call void asm sideeffect "bl $0", "X"(void ()* nonnull @f4)
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ret void
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}
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declare void @foo(...)
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; This tests the behavior of the X constraint when used on functions pointers,
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; or functions with a cast. In the first asm call we figure out that this
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; is a function pointer and emit the label. However, in the second asm call
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; we can't see through the bitcast and we end up having to lower this constraint
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; to something else. This is not ideal, but it is a correct behaviour according
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; to the definition of the X constraint.
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;
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; In this case (and other cases where we could have emitted something else),
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; what we're doing with the X constraint is not particularly useful either,
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; since the user could have used "r" in this situation for the same effect.
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; CHECK-LABEL: f6
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; CHECK: bl foo
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; CHECK: br x
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define void @f6() nounwind {
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entry:
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tail call void asm sideeffect "bl $0", "X"(void (...)* @foo) nounwind
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tail call void asm sideeffect "br $0", "X"(void (...)* bitcast (void ()* @f4 to void (...)*)) nounwind
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ret void
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}
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; The following IR can be generated from C code with a function like:
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; void a() {
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; void* a = &&A;
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; asm volatile ("bl %0" : : "X" (a));
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; A:
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; return;
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; }
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;
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; Ideally this would give the block address of bb, but it requires us to see
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; through blockaddress, which we can't do at the moment. This might break some
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; existing use cases where a user would expect to get a block label and instead
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; gets the block address in a register. However, note that according to the
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; "no constraints" definition this behaviour is correct (although not very nice).
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; CHECK-LABEL: f7
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; CHECK: bl
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define void @f7() {
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call void asm sideeffect "br $0", "X"( i8* blockaddress(@f7, %bb) )
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br label %bb
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bb:
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ret void
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}
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; If we use a constraint "=*X", we should get a store back to *%x (in x0).
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; CHECK-LABEL: f8
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; CHECK: add [[Dest:x[0-9]+]], x0, x0
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; CHECK: str [[Dest]], [x0]
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define void @f8(i64 *%x) {
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entry:
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tail call void asm sideeffect "add $0, x0, x0", "=*X"(i64 *%x)
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ret void
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}
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