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1652ed61e6
I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
228 lines
7.3 KiB
LLVM
228 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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define <vscale x 16 x i8> @test_lane0_16xi8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: test_lane0_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl1
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.b, p0/m, w8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 0
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ret <vscale x 16 x i8> %b
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}
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define <vscale x 8 x i16> @test_lane0_8xi16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: test_lane0_8xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl1
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.h, p0/m, w8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 8 x i16> %a, i16 30, i32 0
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ret <vscale x 8 x i16> %b
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}
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define <vscale x 4 x i32> @test_lane0_4xi32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: test_lane0_4xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl1
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.s, p0/m, w8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 4 x i32> %a, i32 30, i32 0
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ret <vscale x 4 x i32> %b
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}
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define <vscale x 2 x i64> @test_lane0_2xi64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: test_lane0_2xi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.d, p0/m, x8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 2 x i64> %a, i64 30, i32 0
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ret <vscale x 2 x i64> %b
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}
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define <vscale x 2 x double> @test_lane0_2xf64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: test_lane0_2xf64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d1, #1.00000000
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 2 x double> %a, double 1.0, i32 0
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ret <vscale x 2 x double> %b
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}
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define <vscale x 4 x float> @test_lane0_4xf32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: test_lane0_4xf32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, #1.00000000
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; CHECK-NEXT: ptrue p0.s, vl1
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; CHECK-NEXT: mov z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 4 x float> %a, float 1.0, i32 0
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ret <vscale x 4 x float> %b
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}
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define <vscale x 8 x half> @test_lane0_8xf16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: test_lane0_8xf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov h1, #1.00000000
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; CHECK-NEXT: ptrue p0.h, vl1
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; CHECK-NEXT: mov z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 8 x half> %a, half 1.0, i32 0
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ret <vscale x 8 x half> %b
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}
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; Undefined lane insert
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define <vscale x 2 x i64> @test_lane4_2xi64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: test_lane4_2xi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: index z1.d, #0, #1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov z2.d, x8
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; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.d, p0/m, x8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 2 x i64> %a, i64 30, i32 4
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ret <vscale x 2 x i64> %b
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}
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; Undefined lane insert
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define <vscale x 8 x half> @test_lane9_8xf16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: test_lane9_8xf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #9
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; CHECK-NEXT: index z1.h, #0, #1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: mov z2.h, w8
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; CHECK-NEXT: cmpeq p0.h, p0/z, z1.h, z2.h
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; CHECK-NEXT: fmov h1, #1.00000000
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; CHECK-NEXT: mov z0.h, p0/m, h1
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 8 x half> %a, half 1.0, i32 9
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ret <vscale x 8 x half> %b
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}
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define <vscale x 16 x i8> @test_lane1_16xi8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: test_lane1_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: index z1.b, #0, #1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: mov z2.b, w8
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; CHECK-NEXT: cmpeq p0.b, p0/z, z1.b, z2.b
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.b, p0/m, w8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 1
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ret <vscale x 16 x i8> %b
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}
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define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) {
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; CHECK-LABEL: test_lanex_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sxtw x8, w0
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; CHECK-NEXT: index z1.b, #0, #1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: mov z2.b, w8
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; CHECK-NEXT: cmpeq p0.b, p0/z, z1.b, z2.b
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; CHECK-NEXT: mov w8, #30
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; CHECK-NEXT: mov z0.b, p0/m, w8
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 %x
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ret <vscale x 16 x i8> %b
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}
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; Redundant lane insert
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define <vscale x 4 x i32> @extract_insert_4xi32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: extract_insert_4xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = extractelement <vscale x 4 x i32> %a, i32 2
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%c = insertelement <vscale x 4 x i32> %a, i32 %b, i32 2
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 8 x i16> @test_lane6_undef_8xi16(i16 %a) {
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; CHECK-LABEL: test_lane6_undef_8xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #6
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; CHECK-NEXT: index z0.h, #0, #1
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; CHECK-NEXT: mov z1.h, w8
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p0/m, w0
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 8 x i16> undef, i16 %a, i32 6
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ret <vscale x 8 x i16> %b
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}
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define <vscale x 16 x i8> @test_lane0_undef_16xi8(i8 %a) {
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; CHECK-LABEL: test_lane0_undef_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: ret
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%b = insertelement <vscale x 16 x i8> undef, i8 %a, i32 0
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ret <vscale x 16 x i8> %b
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}
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define <vscale x 16 x i8> @test_insert0_of_extract0_16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: test_insert0_of_extract0_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z1.b, b1
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; CHECK-NEXT: ptrue p0.b, vl1
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: mov z0.b, p0/m, w8
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; CHECK-NEXT: ret
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%c = extractelement <vscale x 16 x i8> %b, i32 0
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%d = insertelement <vscale x 16 x i8> %a, i8 %c, i32 0
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ret <vscale x 16 x i8> %d
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}
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define <vscale x 16 x i8> @test_insert64_of_extract64_16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: test_insert64_of_extract64_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #64
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; CHECK-NEXT: index z2.b, #0, #1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: whilels p1.b, xzr, x8
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; CHECK-NEXT: mov z3.b, w8
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; CHECK-NEXT: lastb w8, p1, z1.b
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; CHECK-NEXT: cmpeq p0.b, p0/z, z2.b, z3.b
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; CHECK-NEXT: mov z0.b, p0/m, w8
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; CHECK-NEXT: ret
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%c = extractelement <vscale x 16 x i8> %b, i32 64
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%d = insertelement <vscale x 16 x i8> %a, i8 %c, i32 64
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ret <vscale x 16 x i8> %d
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}
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define <vscale x 16 x i8> @test_insert3_of_extract1_16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: test_insert3_of_extract1_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z1.b, z1.b[1]
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; CHECK-NEXT: mov w8, #3
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; CHECK-NEXT: index z2.b, #0, #1
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: mov z1.b, w8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmpeq p0.b, p0/z, z2.b, z1.b
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; CHECK-NEXT: mov z0.b, p0/m, w9
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; CHECK-NEXT: ret
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%c = extractelement <vscale x 16 x i8> %b, i32 1
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%d = insertelement <vscale x 16 x i8> %a, i8 %c, i32 3
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ret <vscale x 16 x i8> %d
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}
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