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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
183 lines
5.2 KiB
LLVM
183 lines
5.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; INDEX (IMMEDIATES)
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;
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define <vscale x 16 x i8> @index_ii_i8() {
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; CHECK-LABEL: index_ii_i8:
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; CHECK: index z0.b, #-16, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 -16, i8 15)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ii_i16() {
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; CHECK-LABEL: index_ii_i16:
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; CHECK: index z0.h, #15, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 15, i16 -16)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ii_i32() {
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; CHECK-LABEL: index_ii_i32:
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; CHECK: index z0.s, #-16, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 -16, i32 15)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ii_i64() {
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; CHECK-LABEL: index_ii_i64:
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; CHECK: index z0.d, #15, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 15, i64 -16)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @index_ii_range() {
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; CHECK-LABEL: index_ii_range:
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; CHECK: mov w8, #16
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; CHECK-NEXT: mov x9, #-17
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; CHECK-NEXT: index z0.d, x9, x8
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 -17, i64 16)
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ret <vscale x 2 x i64> %out
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}
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;
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; INDEX (IMMEDIATE, SCALAR)
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;
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define <vscale x 16 x i8> @index_ir_i8(i8 %a) {
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; CHECK-LABEL: index_ir_i8:
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; CHECK: index z0.b, #15, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 15, i8 %a)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ir_i16(i16 %a) {
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; CHECK-LABEL: index_ir_i16:
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; CHECK: index z0.h, #-16, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 -16, i16 %a)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ir_i32(i32 %a) {
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; CHECK-LABEL: index_ir_i32:
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; CHECK: index z0.s, #15, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 15, i32 %a)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ir_i64(i64 %a) {
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; CHECK-LABEL: index_ir_i64:
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; CHECK: index z0.d, #-16, x0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 -16, i64 %a)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @index_ir_range(i32 %a) {
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; CHECK-LABEL: index_ir_range:
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; CHECK: mov w8, #-17
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; CHECK: index z0.s, w8, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 -17, i32 %a)
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ret <vscale x 4 x i32> %out
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}
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;
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; INDEX (SCALAR, IMMEDIATE)
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;
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define <vscale x 16 x i8> @index_ri_i8(i8 %a) {
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; CHECK-LABEL: index_ri_i8:
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; CHECK: index z0.b, w0, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %a, i8 -16)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_ri_i16(i16 %a) {
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; CHECK-LABEL: index_ri_i16:
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; CHECK: index z0.h, w0, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 15)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_ri_i32(i32 %a) {
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; CHECK-LABEL: index_ri_i32:
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; CHECK: index z0.s, w0, #-16
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %a, i32 -16)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_ri_i64(i64 %a) {
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; CHECK-LABEL: index_ri_i64:
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; CHECK: index z0.d, x0, #15
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %a, i64 15)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x i16> @index_ri_range(i16 %a) {
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; CHECK-LABEL: index_ri_range:
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; CHECK: mov w8, #16
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; CHECK: index z0.h, w0, w8
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 16)
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ret <vscale x 8 x i16> %out
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}
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;
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; INDEX (SCALARS)
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;
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define <vscale x 16 x i8> @index_rr_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: index_rr_i8:
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; CHECK: index z0.b, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %a, i8 %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @index_rr_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: index_rr_i16:
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; CHECK: index z0.h, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %a, i16 %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @index_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: index_rr_i32:
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; CHECK: index z0.s, w0, w1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %a, i32 %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @index_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: index_rr_i64:
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; CHECK: index z0.d, x0, x1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %a, i64 %b)
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ret <vscale x 2 x i64> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64)
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