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54d477baad
Summary:
This patch adds the following LLVM IR intrinsics for SVE:
1. non-temporal gather loads
* @llvm.aarch64.sve.ldnt1.gather
* @llvm.aarch64.sve.ldnt1.gather.uxtw
* @llvm.aarch64.sve.ldnt1.gather.scalar.offset
2. non-temporal scatter stores
* @llvm.aarch64.sve.stnt1.scatter
* @llvm.aarch64.sve.ldnt1.gather.uxtw
* @llvm.aarch64.sve.ldnt1.gather.scalar.offset
These intrinsic are mapped to the corresponding SVE instructions
(example for half-words, zero-extending):
* ldnt1h { z0.s }, p0/z, [z0.s, x0]
* stnt1h { z0.s }, p0/z, [z0.s, x0]
Note that for non-temporal gathers/scatters, the SVE spec defines only
one instruction type: "vector + scalar". For this reason, we swap the
arguments when processing intrinsics that implement the "scalar +
vector" addressing mode:
* @llvm.aarch64.sve.ldnt1.gather
* @llvm.aarch64.sve.ldnt1.gather.uxtw
* @llvm.aarch64.sve.stnt1.scatter
* @llvm.aarch64.sve.ldnt1.gather.uxtw
In other words, all intrinsics for gather-loads and scatter-stores
implemented in this patch are mapped to the same load and store
instruction, respectively.
The sve2_mem_gldnt_vs multiclass (and it's counterpart for scatter
stores) from SVEInstrFormats.td was split into:
* sve2_mem_gldnt_vec_vs_32_ptrs (32bit wide base addresses)
* sve2_mem_gldnt_vec_vs_62_ptrs (64bit wide base addresses)
This is consistent with what we did for
@llvm.aarch64.sve.ld1.scalar.offset and highlights the actual split in
the spec and the implementation.
Reviewed by: sdesmalen
Differential Revision: https://reviews.llvm.org/D74858
135 lines
7.2 KiB
LLVM
135 lines
7.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; STNT1B, STNT1W, STNT1H, STNT1D: vector base + scalar offset
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; stnt1b { z0.s }, p0/z, [z0.s, x0]
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;
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; STNT1B
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define void @stnt1b_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: stnt1b_s:
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; CHECK: stnt1b { z0.s }, p0, [z1.s, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8> %data_trunc,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret void
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}
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define void @stnt1b_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: stnt1b_d:
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; CHECK: stnt1b { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i8> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret void
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}
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; STNT1H
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define void @stnt1h_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: stnt1h_s:
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; CHECK: stnt1h { z0.s }, p0, [z1.s, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %data_trunc,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret void
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}
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define void @stnt1h_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: stnt1h_d:
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; CHECK: stnt1h { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret void
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}
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; STNT1W
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define void @stnt1w_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: stnt1w_s:
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; CHECK: stnt1w { z0.s }, p0, [z1.s, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret void
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}
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define void @stnt1w_f32_s(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: stnt1w_f32_s:
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; CHECK: stnt1w { z0.s }, p0, [z1.s, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret void
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}
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define void @stnt1w_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: stnt1w_d:
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; CHECK: stnt1w { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret void
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}
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; STNT1D
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define void @stnt1d_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: stnt1d_d:
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; CHECK: stnt1d { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret void
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}
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define void @stnt1d_f64_d(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: stnt1d_f64_d:
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; CHECK: stnt1d { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret void
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}
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; STNT1B
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i8>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; STNT1H
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i16>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; STNT1W
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; STNT1D
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f32.nxv2i64(<vscale x 2 x float>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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