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ae49303684
Summary: Remove option guarding support of quad precision operations. Reviewers: nemanjai, #powerpc, steven.zhang Reviewed By: nemanjai, #powerpc, steven.zhang Subscribers: qiucf, wuzish, nemanjai, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D83437
52 lines
1.6 KiB
LLVM
52 lines
1.6 KiB
LLVM
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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; Function Attrs: norecurse nounwind readnone
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define i64 @getPart1(fp128 %in) local_unnamed_addr {
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entry:
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%0 = bitcast fp128 %in to i128
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%a.sroa.0.0.extract.trunc = trunc i128 %0 to i64
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ret i64 %a.sroa.0.0.extract.trunc
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; CHECK-LABEL: getPart1
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; CHECK: mfvsrld r3, v2
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: getPart1
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; CHECK-BE: mfvsrld r3, v2
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; CHECK-BE-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @getPart2(fp128 %in) local_unnamed_addr {
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entry:
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%0 = bitcast fp128 %in to i128
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%a.sroa.0.8.extract.shift = lshr i128 %0, 64
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%a.sroa.0.8.extract.trunc = trunc i128 %a.sroa.0.8.extract.shift to i64
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ret i64 %a.sroa.0.8.extract.trunc
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; CHECK-LABEL: getPart2
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; CHECK: mfvsrd r3, v2
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: getPart2
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; CHECK-BE: mfvsrd r3, v2
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; CHECK-BE-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @checkBitcast(fp128 %in, <2 x i64> %in2, <2 x i64> *%out) local_unnamed_addr {
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entry:
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%0 = bitcast fp128 %in to <2 x i64>
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%1 = extractelement <2 x i64> %0, i64 0
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%2 = add <2 x i64> %0, %in2
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store <2 x i64> %2, <2 x i64> *%out, align 16
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ret i64 %1
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; CHECK-LABEL: checkBitcast
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; CHECK: mfvsrld r3, v2
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; CHECK: blr
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; CHECK-BE-LABEL: checkBitcast
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; CHECK-BE: mfvsrd r3, v2
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; CHECK-BE: blr
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}
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