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https://github.com/RPCS3/llvm-mirror.git
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535690cd25
Change to expand MULHU/MULHS/UMUL_LOHI/SMUL_LOHI for i32 and i64 since those instructions are not available on Aurora SX VE. Some of them are used in expansion of i128 multiply, so need to modify them to support i128. Then, update basic arithmetic regression tests of i128 and signed/unsigned i32 typed integer values. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85490
302 lines
8.6 KiB
LLVM
302 lines
8.6 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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; Function Attrs: norecurse nounwind readnone
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define i128 @remi128(i128 %a, i128 %b) {
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; CHECK-LABEL: remi128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s4, __modti3@lo
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; CHECK-NEXT: and %s4, %s4, (32)0
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; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s4)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i128 %a, %b
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ret i128 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remi64(i64 %a, i64 %b) {
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; CHECK-LABEL: remi64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s2, %s0, %s1
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; CHECK-NEXT: muls.l %s1, %s2, %s1
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; CHECK-NEXT: subs.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i64 %a, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @remi32(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: remi32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i32 %a, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @remu128(i128 %a, i128 %b) {
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; CHECK-LABEL: remu128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s4, __umodti3@lo
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; CHECK-NEXT: and %s4, %s4, (32)0
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; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s4)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i128 %a, %b
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ret i128 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remu64(i64 %a, i64 %b) {
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; CHECK-LABEL: remu64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s2, %s0, %s1
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; CHECK-NEXT: muls.l %s1, %s2, %s1
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; CHECK-NEXT: subs.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i64 %a, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: remu32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i32 %a, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @remi16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: remi16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: or %s11, 0, %s9
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%a32 = sext i16 %a to i32
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%b32 = sext i16 %b to i32
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%r32 = srem i32 %a32, %b32
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%r = trunc i32 %r32 to i16
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ret i16 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: remu16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i16 %a, %b
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ret i16 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @remi8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: remi8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: or %s11, 0, %s9
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%a32 = sext i8 %a to i32
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%b32 = sext i8 %b to i32
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%r32 = srem i32 %a32, %b32
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%r = trunc i32 %r32 to i8
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ret i8 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: remu8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s2, %s0, %s1
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; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i8 %a, %b
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ret i8 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @remi128ri(i128 %a) {
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; CHECK-LABEL: remi128ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s2, __modti3@lo
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s2)
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; CHECK-NEXT: or %s2, 3, (0)1
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; CHECK-NEXT: or %s3, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i128 %a, 3
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ret i128 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remi64ri(i64 %a) {
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; CHECK-LABEL: remi64ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s1, %s0, (62)0
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; CHECK-NEXT: muls.l %s1, 3, %s1
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; CHECK-NEXT: subs.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i64 %a, 3
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @remi32ri(i32 signext %a) {
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; CHECK-LABEL: remi32ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
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; CHECK-NEXT: muls.w.sx %s1, 3, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i32 %a, 3
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @remu128ri(i128 %a) {
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; CHECK-LABEL: remu128ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s2, __umodti3@lo
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s2)
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; CHECK-NEXT: or %s2, 3, (0)1
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; CHECK-NEXT: or %s3, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i128 %a, 3
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ret i128 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remu64ri(i64 %a) {
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; CHECK-LABEL: remu64ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s1, %s0, (62)0
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; CHECK-NEXT: muls.l %s1, 3, %s1
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; CHECK-NEXT: subs.l %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i64 %a, 3
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @remu32ri(i32 zeroext %a) {
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; CHECK-LABEL: remu32ri:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s1, %s0, (62)0
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; CHECK-NEXT: muls.w.sx %s1, 3, %s1
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; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i32 %a, 3
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @remi128li(i128 %a) {
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; CHECK-LABEL: remi128li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s3, 0, %s1
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; CHECK-NEXT: or %s2, 0, %s0
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; CHECK-NEXT: lea %s0, __modti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __modti3@hi(, %s0)
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i128 3, %a
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ret i128 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remi64li(i64 %a, i64 %b) {
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; CHECK-LABEL: remi64li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.l %s0, 3, %s1
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; CHECK-NEXT: muls.l %s0, %s0, %s1
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; CHECK-NEXT: subs.l %s0, 3, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i64 3, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: remi32li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divs.w.sx %s0, 3, %s1
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; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
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; CHECK-NEXT: subs.w.sx %s0, 3, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = srem i32 3, %b
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ret i32 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @remu128li(i128) {
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; CHECK-LABEL: remu128li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s3, 0, %s1
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; CHECK-NEXT: or %s2, 0, %s0
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; CHECK-NEXT: lea %s0, __umodti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __umodti3@hi(, %s0)
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; CHECK-NEXT: or %s0, 3, (0)1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = urem i128 3, %0
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @remu64li(i64 %a, i64 %b) {
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; CHECK-LABEL: remu64li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.l %s0, 3, %s1
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; CHECK-NEXT: muls.l %s0, %s0, %s1
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; CHECK-NEXT: subs.l %s0, 3, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i64 3, %b
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ret i64 %r
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: remu32li:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: divu.w %s0, 3, %s1
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; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
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; CHECK-NEXT: subs.w.sx %s0, 3, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = urem i32 3, %b
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ret i32 %r
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}
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