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272 lines
7.2 KiB
C++
272 lines
7.2 KiB
C++
//===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// \file This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the DAG scheduling mutation to
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// pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MacroFusion.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define DEBUG_TYPE "misched"
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STATISTIC(NumFused, "Number of instr pairs fused");
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using namespace llvm;
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static cl::opt<bool> EnableMacroFusion("x86-misched-fusion", cl::Hidden,
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cl::desc("Enable scheduling for macro fusion."), cl::init(true));
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namespace {
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/// \brief Verify that the instruction pair, First and Second,
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/// should be scheduled back to back. If either instruction is unspecified,
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/// then verify that the other instruction may be part of a pair at all.
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static bool shouldScheduleAdjacent(const X86Subtarget &ST,
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const MachineInstr *First,
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const MachineInstr *Second) {
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// Check if this processor supports macro-fusion. Since this is a minor
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// heuristic, we haven't specifically reserved a feature. hasAVX is a decent
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// proxy for SandyBridge+.
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if (!ST.hasAVX())
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return false;
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enum {
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FuseTest,
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FuseCmp,
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FuseInc
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} FuseKind;
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assert((First || Second) && "At least one instr must be specified");
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unsigned FirstOpcode = First
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? First->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = Second
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? Second->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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switch (SecondOpcode) {
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default:
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return false;
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case X86::JE_1:
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case X86::JNE_1:
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case X86::JL_1:
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case X86::JLE_1:
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case X86::JG_1:
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case X86::JGE_1:
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FuseKind = FuseInc;
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break;
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case X86::JB_1:
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case X86::JBE_1:
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case X86::JA_1:
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case X86::JAE_1:
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FuseKind = FuseCmp;
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break;
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case X86::JS_1:
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case X86::JNS_1:
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case X86::JP_1:
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case X86::JNP_1:
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case X86::JO_1:
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case X86::JNO_1:
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FuseKind = FuseTest;
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break;
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}
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switch (FirstOpcode) {
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default:
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return false;
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case X86::TEST8rr:
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case X86::TEST16rr:
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case X86::TEST32rr:
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case X86::TEST64rr:
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case X86::TEST8ri:
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case X86::TEST16ri:
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case X86::TEST32ri:
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case X86::TEST32i32:
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case X86::TEST64i32:
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case X86::TEST64ri32:
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case X86::TEST8rm:
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case X86::TEST16rm:
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case X86::TEST32rm:
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case X86::TEST64rm:
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case X86::TEST8ri_NOREX:
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case X86::AND16i16:
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case X86::AND16ri:
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case X86::AND16ri8:
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case X86::AND16rm:
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case X86::AND16rr:
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case X86::AND32i32:
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case X86::AND32ri:
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case X86::AND32ri8:
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case X86::AND32rm:
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case X86::AND32rr:
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case X86::AND64i32:
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case X86::AND64ri32:
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case X86::AND64ri8:
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case X86::AND64rm:
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case X86::AND64rr:
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case X86::AND8i8:
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case X86::AND8ri:
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case X86::AND8rm:
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case X86::AND8rr:
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return true;
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case X86::CMP16i16:
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP16rm:
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case X86::CMP16rr:
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case X86::CMP32i32:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP32rm:
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case X86::CMP32rr:
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case X86::CMP64i32:
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP64rm:
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case X86::CMP64rr:
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case X86::CMP8i8:
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case X86::CMP8ri:
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case X86::CMP8rm:
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case X86::CMP8rr:
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case X86::ADD16i16:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri8_DB:
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case X86::ADD16ri_DB:
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case X86::ADD16rm:
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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case X86::ADD32i32:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri8_DB:
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case X86::ADD32ri_DB:
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case X86::ADD32rm:
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case X86::ADD32rr:
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case X86::ADD32rr_DB:
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case X86::ADD64i32:
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case X86::ADD64ri32:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8:
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case X86::ADD64ri8_DB:
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case X86::ADD64rm:
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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case X86::ADD8i8:
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case X86::ADD8mi:
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case X86::ADD8mr:
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case X86::ADD8ri:
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case X86::ADD8rm:
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case X86::ADD8rr:
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case X86::SUB16i16:
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case X86::SUB16ri:
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case X86::SUB16ri8:
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case X86::SUB16rm:
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case X86::SUB16rr:
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case X86::SUB32i32:
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case X86::SUB32ri:
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case X86::SUB32ri8:
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case X86::SUB32rm:
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case X86::SUB32rr:
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case X86::SUB64i32:
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case X86::SUB64ri32:
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case X86::SUB64ri8:
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case X86::SUB64rm:
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case X86::SUB64rr:
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case X86::SUB8i8:
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case X86::SUB8ri:
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case X86::SUB8rm:
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case X86::SUB8rr:
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return FuseKind == FuseCmp || FuseKind == FuseInc;
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case X86::INC16r:
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case X86::INC32r:
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case X86::INC64r:
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case X86::INC8r:
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case X86::DEC16r:
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case X86::DEC32r:
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case X86::DEC64r:
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case X86::DEC8r:
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return FuseKind == FuseInc;
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case X86::INSTRUCTION_LIST_END:
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return true;
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}
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}
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/// \brief Post-process the DAG to create cluster edges between instructions
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/// that may be fused by the processor into a single operation.
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class X86MacroFusion : public ScheduleDAGMutation {
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public:
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X86MacroFusion() {}
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void apply(ScheduleDAGInstrs *DAGInstrs) override;
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};
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void X86MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
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ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
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const X86Subtarget &ST = DAG->MF.getSubtarget<X86Subtarget>();
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// For now, assume targets can only fuse with the branch.
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SUnit &ExitSU = DAG->ExitSU;
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MachineInstr *Branch = ExitSU.getInstr();
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if (!Branch || !shouldScheduleAdjacent(ST, nullptr, Branch))
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return;
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for (SDep &PredDep : ExitSU.Preds) {
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if (PredDep.isWeak())
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continue;
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SUnit &SU = *PredDep.getSUnit();
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MachineInstr &Pred = *SU.getInstr();
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if (!shouldScheduleAdjacent(ST, &Pred, Branch))
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continue;
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// Create a single weak edge from SU to ExitSU. The only effect is to cause
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// bottom-up scheduling to heavily prioritize the clustered SU. There is no
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// need to copy predecessor edges from ExitSU to SU, since top-down
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// scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
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// of SU, we could create an artificial edge from the deepest root, but it
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// hasn't been needed yet.
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bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster));
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(void)Success;
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assert(Success && "No DAG nodes should be reachable from ExitSU");
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// Adjust latency of data deps between the nodes.
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for (SDep &PredDep : ExitSU.Preds)
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if (PredDep.getSUnit() == &SU)
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PredDep.setLatency(0);
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for (SDep &SuccDep : SU.Succs)
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if (SuccDep.getSUnit() == &ExitSU)
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SuccDep.setLatency(0);
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++NumFused;
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DEBUG(dbgs() << DAG->MF.getName() << "(): Macro fuse ";
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SU.print(dbgs(), DAG);
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dbgs() << " - ExitSU"
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<< " / " << DAG->TII->getName(Pred.getOpcode()) << " - "
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<< DAG->TII->getName(Branch->getOpcode()) << '\n';);
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break;
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}
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}
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} // end namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createX86MacroFusionDAGMutation () {
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return EnableMacroFusion ? make_unique<X86MacroFusion>() : nullptr;
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}
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} // end namespace llvm
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