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Summary: Proposal and roadmap towards vector predication in LLVM. This patch documents that a) It is recognized that current LLVM is ill-equipped for vector predication. b) The community is working on a solution. c) A concrete prototype exists in the VP extension (D57504). Reviewers: rkruppe, rengolin, cameron.mcinally, SjoerdMeijer, andrew.w.kaylor, craig.topper, sdesmalen, k-ishizaka, lattner, fhahn Reviewed By: andrew.w.kaylor Subscribers: rogfer01, merge_guards_bot, simoncook, s.egerton, llvm-commits, efocht Tags: #llvm Differential Revision: https://reviews.llvm.org/D73889
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3.0 KiB
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89 lines
3.0 KiB
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==========================
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Vector Predication Roadmap
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==========================
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.. contents:: Table of Contents
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:depth: 3
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:local:
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Motivation
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==========
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This proposal defines a roadmap towards native vector predication in LLVM,
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specifically for vector instructions with a mask and/or an explicit vector
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length. LLVM currently has no target-independent means to model predicated
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vector instructions for modern SIMD ISAs such as AVX512, ARM SVE, the RISC-V V
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extension and NEC SX-Aurora. Only some predicated vector operations, such as
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masked loads and stores, are available through intrinsics [MaskedIR]_.
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The Vector Predication (VP) extensions is a concrete RFC and prototype
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implementation to achieve native vector predication in LLVM. The VP prototype
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and all related discussions can be found in the VP patch on Phabricator
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[VPRFC]_.
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Roadmap
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=======
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1. IR-level VP intrinsics
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-------------------------
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- There is a consensus on the semantics/instruction set of VP.
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- VP intrinsics and attributes are available on IR level.
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- TTI has capability flags for VP (``supportsVP()``?,
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``haveActiveVectorLength()``?).
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Result: VP usable for IR-level vectorizers (LV, VPlan, RegionVectorizer),
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potential integration in Clang with builtins.
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2. CodeGen support
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------------------
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- VP intrinsics translate to first-class SDNodes
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(eg ``llvm.vp.fdiv.* -> vp_fdiv``).
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- VP legalization (legalize explicit vector length to mask (AVX512), legalize VP
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SDNodes to pre-existing ones (SSE, NEON)).
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Result: Backend development based on VP SDNodes.
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3. Lift InstSimplify/InstCombine/DAGCombiner to VP
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--------------------------------------------------
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- Introduce PredicatedInstruction, PredicatedBinaryOperator, .. helper classes
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that match standard vector IR and VP intrinsics.
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- Add a matcher context to PatternMatch and context-aware IR Builder APIs.
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- Incrementally lift DAGCombiner to work on VP SDNodes as well as on regular
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vector instructions.
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- Incrementally lift InstCombine/InstSimplify to operate on VP as well as
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regular IR instructions.
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Result: Optimization of VP intrinsics on par with standard vector instructions.
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4. Deprecate llvm.masked.* / llvm.experimental.reduce.*
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-------------------------------------------------------
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- Modernize llvm.masked.* / llvm.experimental.reduce* by translating to VP.
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- DCE transitional APIs.
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Result: VP has superseded earlier vector intrinsics.
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5. Predicated IR Instructions
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-----------------------------
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- Vector instructions have an optional mask and vector length parameter. These
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lower to VP SDNodes (from Stage 2).
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- Phase out VP intrinsics, only keeping those that are not equivalent to
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vectorized scalar instructions (reduce, shuffles, ..)
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- InstCombine/InstSimplify expect predication in regular Instructions (Stage (3)
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has laid the groundwork).
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Result: Native vector predication in IR.
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References
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==========
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.. [MaskedIR] `llvm.masked.*` intrinsics,
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https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics
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.. [VPRFC] RFC: Prototype & Roadmap for vector predication in LLVM,
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https://reviews.llvm.org/D57504
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